Part Number: TLK2711-SP
Hello,
My current TLK2711 test setup is as below which is Xilinx FPGA transfer(TX) data to TLK2711 and received data is sent to another FPGA on the same board.
So TLK2711 is used by only RX mode.
And receiver configuration of TLK2711 is as below.
As far as I know, CML to VML interface is supported if proper biasing is set and TLK2711 has integrated termination resistor on RX side.
So the user doesn't have to put termination resistor externally. Is it correct?
And I measured resistance RXP(57) with RXN(56). It measured nearly 75ohm.
Also, I measured resistance RXP(57) with VDDA(59, 61). I thought it should be 4k ohm but it was measured open. Is it correct?
So my point is that I sent IDLE data(K28.5/D5.6) from Xilinx FPGA to TLK2711 and the received parallel data (RXD) was different from what I expected.
It should be C5BC(K28.5/D5.6) on RXD but the real data is quite different as below. (Below is logic analyzer display and only captured Lower 8-bit of RXD.)
I also tested PRBS pattern loopback mode and the result is as below. I think loopback mode looks okay. 
And I use Q-Tech oscillator for GTX_CLK. Its Jitter RMS is 8ps (typ.). I don't know why received data is different. Any idea solving this problem?
Best regards,
Ethan
