Hi all
Would you mind if we ask DP83822IF?
There is the description "The DP83822 requires Clock to be present at PoR. In case clock is delayed, pull-down on XI is recommended to avoid spurious signal latch-up." on the datasheet P94.
How much does the value of pull-down recommend for it?
Does it require for situation of floating?
We assume that it requires to be fixed logic level high or low, right?
If our recognition is correct, we quess that pull-down is more than 10kohm or 100kohm.
Kind regards,
Hirotaka Matsumoto