Hi Team,
My customer are connecting 4 Lanes from DS80PCI402 device to Xilinx UltraScle FPGA SerDes.
The distance between the DS80PCI402 device to Xilinx UltraScle FPGA is about 10 inches
- What is the recommended setting for RXDET pin and what are the considerations for this termination setting?
- What is the recommended setting for SD_TH pin and what are the considerations for this thresholds setting?
Do you know about some electrical limitation (ERRATA) of the device that they should know.
Can you approve that the Max Differential RX peak-to-peak is 1.2 V voltage (VID) and that there is no Limitation with this value.
Thanks,
Shlomi