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DS90UB941AS-Q1: DSI input problems

Peter Fitger
Prodigy 20 points
Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: DS90UB948-Q1

It seems like I can not get the DSI input to the serializer to work properly.

Reported errors:
- DSI Port 0 indirect register 28 - DSI CRC Checksum error - Constantly active
- DSI Port 0 indirect register 0 - Error counter is constantly 0 (Why, if we constantly have errors?)
- Register 5A bit 2 = 0. DSI PLL Not locked. (Should be locked?)
- DSI Port 0 indirect register 3A/3B - Indicates M/N = 2/3, should be 1/3?

Maybe there is something more I have missed

Serializer setup:
Single mode (Single DSI input, single output)
Continuous DSI clock as Bridge clocking mode.

DSI input:
1920 x 720 pixels, 24-bit RGB
Pixel clocks of 95, 91 and 66 MHz has been tested - no difference.
Register readouts are from 66 MHz test.
4 - lane DSI.
Sync signals.

Receiver end is a DS90UB948-Q1 deserializer.

Complete register readout:

Serializer main registers
00: 24 00 00 9A 10 00 58 00
08: 00 01 41 0A 47 30 00 00
10: 00 00 00 BB 00 00 FE 1E
18: 7F 7F 01 00 00 00 01 00
20: 0B 00 25 00 00 00 00 00
28: 01 20 20 A0 00 00 A5 5A
30: 00 09 00 05 0C 00 00 00
38: 00 00 00 00 00 00 81 02
40: 09 3F 00 00 00 00 00 00
48: 00 00 00 00 00 00 00 8C
50: 16 00 00 00 00 00 00 02
58: 00 00 D9 81 07 06 44 42
60: 22 02 00 00 10 00 00 00
68: 00 00 00 00 00 00 20 00
70: 00 00 00 00 00 00 00 00
78: 00 00 00 00 00 00 7E 00

DSI Port 0 indirect registers
00: 00 00 00 18 1C 10 00 00
08: 00 00 00 00 00 00 00 1F
10: 00 00 00 00 00 00 00 00
18: 00 00 00 00 00 00 00 00
20: 7F 60 FF 7F 00 00 00 00
28: 01 FF 3E 04 00 00 00 00
30: 00 20 00 04 00 20 00 00
38: 00 00 02 03 00 00 00 00

DSI Port 1 indirect registers
00: 00 00 00 18 1C 10 00 00
08: 00 00 00 00 00 00 00 10
10: 00 00 00 00 00 00 00 00
18: 00 00 00 00 00 00 00 00
20: 7F 60 FF 7F 00 00 00 00
28: 00 00 00 00 00 00 00 00
30: 00 20 00 04 00 20 00 00
38: 00 00 02 03 00 00 00 00

I have tried to change DSI timing parameters.
This can make DPHY errors appear, but does not seem to get anything else better.

Anya ideas?

/Peter

  • 0
    TI__Expert 5480 points

    Hi Peter, 

    Can you give me some more system details? 

    You say your resolution is 1920 x 720. What is the pclk and why are you testing out different pclks? The pclk = horizontal total (active + banking) * vertical total (active + blanking) * fps.
    Are you using single DSI input with single FPD output/ dual FPD output/  Splitter ouptut/ Independent mode? 
    What clock reference are you using? DSI clock reference mode or external clock? 
    Are you using DSI burst/non burst mode with sync event/pulse mode? 

    Also what is the value for 0x5a[7]? 

  • 0 in reply to Sally Cheung95
    TI__Intellectual 2930 points

    Hello Peter

     Can you also clarify what SoC you are using and whether the SoC output had been checked for DSI compliance?

    Thanks

    Vijay

  • 0 in reply to Vijaya Ceekala
    Prodigy 20 points

    We have solved the basic problem (bad DSI output from our Xilinx Zync Ultrascale+)

    Changing bandwith was done to use the same values as our eval kit used, to remove other possible errors.

    We are using forced single mode (One DSI in, one FPD out)

    These issues still remain - but as it works I will not put in any time in solving this:

    DSI Port 0 indirect register 28 - DSI CRC Checksum error - Constantly active
    DSI Port 0 indirect register 0 - Error counter is constantly 0 (Why, if we constantly have errors?)

    /Peter

  • 0 in reply to Peter Fitger
    TI__Expert 5480 points

    Do you have the error register enabled?