DP83867IR: not working at 100/1000Mbps but works at 10Mbps

Hi Annamol,

Please allow some time to review your layout and schematic.

Thank you,

Nikhil

Hi Annamol,

Are you able to read/write registers to advertise only 100/1000 Mbps speed? How are you currently configuring the device for 10/100/1000 Mbps? It looks like you are using 1k strap resistors. Please use the recommended strap modes and resistances as seen in section 8.5 of the datasheet. You may be strapping the device into an unknown or floating state. RX_CTRL requires a strap in either mode 3 or 4. Please fix strap resistors and let me know if you are still running into issues. 

It looks like the traces for the differential pairs have been length matched and should be ok.  

Thank you,

Nikhil 

Hi Annamol,

I will be closing this thread. If you are still having issues, please open a new thread.

Thank you,

Nikhil

Hi Nikhil,

Sorry for the delayed response. Our development environment is in petalinux from Xilinx. For configuring the PHY for various speeds say 10/100/1000Mbps, from vivado environment we adjust the PLL clock frequency as 2.5/25/125MHz. The device tree mentioned in our petalinux project is listed below

&gem0{
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id"; pinctrl-names = "default";
phy-reset-gpio = <&gpio0 11 0>;
phy-reset-active-low;
phy0: phy@12 {
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
reg = <12>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x01>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
status = "okay";
};
};

Apart from these, we are not making any changes. This is the 3rd spin of the same design (v1,v2,v3), the same settings of strap resistors were used in V2 and V3. V2 works perfectly and V3 works only at 10Mbps. The only change from v2 to v3 was the addition of ESD section onto the working v2 design.  We have attached schematics of v2 design as well. 

ethernet v2.pdf

Hi Annamol,

Can you share the v3 schematic with me?

I understand you have v2 working. However, configuring PHY speeds is typically done through either register settings or strap settings. We have not tested changing the PLL clock frequency as you are doing. As a check, can you use register 0 to force 100/1000 Mbps and see if you are able to establish link? Additionally, can you use register 4 to advertise only 100/1000 Mbps and see if you are able to establish link? Please read back bits [15:14] of register 11 to determine what speed the PHY has been set to after each step, as well as after changing the PLL frequency.

Again, I understand the v2 design was working, but I still recommend using the correct strap resistor configurations as described by the datasheet. Without fixing this issue, the unknown will remain in the design. 

Thank you,

Nikhil

Hi, 

The main difference between V2 and V3 is the addition of ESD diodes. We have attached the schematics of V3 for your reference. Meanwhile, we will try making the changes as suggested by you in strap and register settings and check if there is any difference in connection establishment or not. We will let you know the results after testing asap. 1376.25_Ethernet PHY.pdf

Hi Annamol,

Please provide an update when possible.

Thank you,

Nikhil

Hi Nikhil,

Attempt 1 

• The following changes were made in the hardware in strap settings and the various speeds (10/100/1000) were set using ethtool utility (ethtool -s eth0 speed 1000 duplex full autoneg on )

• R61 changed from 1K to 2.7K
• R212 changed from 1K to 1.8K
• R226 changed from 1K to 1.8K

Attempt 2 

• • Take out R212 and leave it open  
  • R61 changed to 2.7K
  • R226 changed to 2.7K 
  • Added a new resistor of 5.76K to RX_CTRL line pulled to 1.8V 

    Please let us know if attempt 2 mentioned above is ok and we are planning to use mii-tool in u-boot mode to check if there is any difference and mii dump for register readback

Hi Annamol,

Can you read back registers 6E and 6F and tell me the results? These registers will let you know if the device is being strapped correctly. Additionally, 

R44-47, the 1k resistors on the TX lines, may be too strong a pull-down. Can you remove them and let me know if you see any changes?

Thank you,

Nikhil