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DP83867IR: MII only mode, TX_CLK stays low

Stefan Glaser1
Prodigy 10 points
Part Number: DP83867IR

Hello, 

I am trying to connect the DP83867 to an FPGA design via MII only. For this specific design, no GMII or RGMII interface is available. 
The PHY is configured for 100/10 MBit only and is connected to a 1GBit switch. After auto-negotiation, the PHY selects a 100MBit connection and RX_CLK is clocked at 25MHz. My problem now is, that TX_CLK stays low all the time.

How can I check if the PHY is actually in MII mode? How can I "force" MII mode and under which conditions the PHY is enabling TX_CLK?

After reading the datasheet for multiple times, I am still not 100% sure if I should actually enable or disable RGMII to get MII mode for 100/10 Mbit connections. 

What does the line "The MAC holds the RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY" actually mean? Another forum post suggests that this refers to TX_CTRL instead of TX_CLK. Do I have to pull TX_CTRL high to enable TX_CLK?

Thank you very much in advance!

Kind regards

Stefan

  • 0
    TI__Genius 11725 points

    Hi Stefan,

    Are you using the 64 pin device? TX_CLK is unused in the VQFN package. To "force" MII mode, you must only advertise 100/10 speed as you have mentioned. Additionally, check that register 10 reads 5048, and bit 7 of register 32 is 0. Please check that link has been established as well (bit 10 of register 11).

    Thank you,

    Nikhil

  • 0 in reply to Nikhil Menon
    Prodigy 140 points

    Hi Nikhil,

    Thank you for your quick response and sorry for my late answer, I was on a holiday,

    Yes, I am using the 64 pin device. I am reading back the following register values:

    PHYSTS = 0x6f02
    PHYCR = 0x5048
    RGMIICTL = 0x0000

    so everything looks as expected.

    RX_CLK is clocking out with 25Mhz which is expected for 100Mbit MII mode, but TX_CLK is still staying low. I also tried to force TX_EN high to start TX_CLK but this was also not working.

    Do you have any other suggestions or things to check?

    Do you have feedback on my previous question concerning the the following line in the datasheet: "The MAC holds the RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY"

    Thank you very much in advance!

    Stefan

  • 0 in reply to Stefan Glaser2
    TI__Genius 11725 points

    Hi Stefan,

    Just to make sure we are covering all bases, can you confirm you are probing TX_CLK (pin 30) and not GTX_CLK (pin 40)? GTX_CLK will remain low in MII mode.

    Thank you,

    Nikhil

  • 0 in reply to Nikhil Menon
    Prodigy 140 points

    Hi Nikhil,

    Yes, I am 100% sure I am probing TX_CLK!
    I also rechecked everything, my footprint, my layout, voltage levels. reset levels, 25MHz clock in, ....
    I am using the dual supply mode, I hope that has nothing to do with it?

    Thank you very much in advance!

    Stefan

  • 0 in reply to Stefan Glaser2
    Prodigy 140 points

    Hi Nikhil,

    My design has two DP83867 PHYs on the PCB so I switched to the other one and I have exactly the same problem.

    I tried 10MBit/s and 100MBit/s modes, I enabled and disabled RGMII and I played with 1000 other register values, in none of the cases the TX_CLK is doing anything. The PHY is receiving packages and clocking them out to the MAC, but the other way around is not working.

    TX_CLK should be a free running clock, I don't quite understand why this signal should be low in any case?

    Thank you very much in advance!

    Stefan

  • 0 in reply to Stefan Glaser2
    TI__Genius 11725 points

    Hi Stefan,

    Can you please share you schematic with me?

    Thank you,

    Nikhil

  • 0 in reply to Nikhil Menon
    Prodigy 140 points

    Hi Nikhil,

    Below is my schematic, RBIAS was already changed to 11k:

  • 0 in reply to Stefan Glaser2
    TI__Genius 11725 points

    Hi Stefan,

    We tried to reproduce this issue in the lab and have seen that TX Clock is functional after writing 0 to register 32. Once I set register 32 to 0, I see TX Clock enabled. How are you accessing the extended registers. Can you read back register 6E and 6F upon power-up, before making any other software changes? These registers indicate what strap modes the PHY has been set to, so we can compare with the schematic. Additionally, please read registers 32 and 31 upon power-up , before making any other changes.

    Thank you,

    Nikhil

  • 0 in reply to Nikhil Menon
    TI__Genius 11725 points

    Hi Stefan,

    Are you able to read back these registers? 

    Thank you,

    Nikhil

  • 0 in reply to Nikhil Menon
    TI__Genius 11725 points

    Hi Stefan,

    I will be closing this thread. If you are still seeing issues, please open a new thread with a link to this one.

    Thank you,

    Nikhil