The RESET pin of the TCA9548A is pulled down and connected to the FPGA. When the power is turned on, RESET goes to a low state, and then goes high with the FPGA. Is there a problem with the usage?
If so, what happens?
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The RESET pin of the TCA9548A is pulled down and connected to the FPGA. When the power is turned on, RESET goes to a low state, and then goes high with the FPGA. Is there a problem with the usage?
If so, what happens?
Hey User,
That should be fine. While the reset pin is held to GND while the FPGA is off, the device will not ACK so any communication to the TCA9548A will not work until the reset pin is pulled high. If you are okay with this (if there is not another master who needs to communicate to a secondary channel through the TCA9548A) then this is okay.
-Bobby