XIO2001: Writing to downstream PCI devices

Edward Lefferd

Part Number: XIO2001

When writing to downstream PCI devices where do I write to in the Configuration Space? I thought I should be writing to in the BARs in the Configuration Space, but this post here https://e2e.ti.com/support/interface/f/138/t/593054 says that it does not have BARs at the specified offsets since it is a bridge in the accepted solution.

over 5 years ago

0 Brian Zhou over 5 years ago

TI__Guru*** 145790 points

Hello,

An engineer has been assigned but response may be delayed due to the holidays.

Regards,

Brian

0 Lee Sledjeski over 5 years ago

TI__Mastermind 43795 points

Hi,

There is some information in the device datasheet in section 8.3.4 and 8.4 about register translation and specific bridge registers.

Regards,

Lee

0 Clemens Ladisch over 5 years ago

Guru 316780 points

The XIO2001 device is a bridge, so it has all the standard bridge registers. In particular, the base/limit registers (1Ch–33h) specify which transactions are passed through to the PCI bus.

This configuration should be handled automatically by the OS. Is there some problem with this in your application?

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XIO2001: Writing to downstream PCI devices