DP83848I: AN0 and AN1 state changes after reset

Hello Sheldon,

Can you confirm that your customer is following all "POWER-UP TIMING" and "RESET TIMING" specifications from "5.6 AC Timing Requirements" section of the datasheet?

Also please confirm that your customer is using a 2.2 k-ohm pullup or pulldown resistor for strapping these, and not connecting directly to ground or Vcc.

"The value set at this input is latched into the DP83848VYB at Hardware-Reset. The float/pulldown status of these pins are latched into the Basic Mode Control Register."

Thanks,

Vibhu

Hi Vibhu,

They are leaving AN0 and AN1 floating in their application so the pull-up resistors should not be a issue. Regarding "POWER-UP TIMING" and "RESET TIMING", could you explain a bit more on how should we check this? Is that determined by hardware or also influenced by software?

Thanks

Sheldon

Vibhu,

They targeting using 100M fully duplex mode but the time point they do hardware reset will influence the final result.

Thanks

Hello Sheldon,

Can you read register ANAR, address 0x04h and see if the register says the straps are latched correctly?

Please refer to "Table 6-13. Negotiation Advertisement Register (ANAR), address 0x04h" to see the bit descriptions of this register. It will tell you what modes are available to the PHY.

Thanks,

Vibhu

Hello Sheldon,

What is the status of this issue?

Thanks,

Vibhu

Hi Vibhu,

I didn't get response from them for the time being. You can close this post first.

Thanks

Sheldon

Will do, please open a new thread referencing this one, when more information is available.

Thanks,

Vibhu