DS90UB949-Q1: HDMI control signals - is 3.3V operation possible?

Alan O

Part Number: DS90UB949-Q1

My customer is designing with the 949A, and their SOC processor has 3.3V I/O buffers for the following HDMI control signals: RX_5V, DDC_SDA, DDC_SCL, and HPD.

They wish to avoid external level translators and want to know if 949A can support 3.3V levels (e.g. pull-up to 3.3V) on these HDMI control pins. Their SOC does not need HDMI spec compliance for these signals.

Can you please confirm the following?

RX_5V: I don't think his input can be driven by 3.3V levels, as the recommended operating range is 4.25V to 5.25V, correct? If so, they should use a level translator for this.
HPD: I think this open-drain output can be pulled-up to 3.3V assuming VOL min spec of 0.4V meets their SOC VIL spec, correct?
DDC_SDA/SCL: I think these open-drain pins could be pulled-up to 3.3V assuming 949A's VIH min spec of 2.7V can be met (may need to scale down Rpu value), correct?

Thanks,
Alan

over 5 years ago

0 Charley Cai over 5 years ago

TI__Genius 12866 points

Hi Alan,

Your assumptions are correct based on the HDMI spec and our 949 datasheet.

HPD, DDC_SDA/SCL should be able to be pulled up to 3.3V assuming 949 VIL/VIH limits are met.

Based on the spec RX_5V is required to be nomial 5V, so they would need a level shifter.

Best Regards,

Charley Cai

0 Alan O over 5 years ago in reply to Charley Cai

TI__Mastermind 32575 points

Thanks Charley.

0 Alan O over 5 years ago in reply to Charley Cai

TI__Mastermind 32575 points

Hi Charley,

Can you confirm the VIH/VIL levels for the DDC inputs?

DDC VIH min spec is 2.7V, but VIL is 0.3 x Vdd,ddc. However, there is no Vdd,ddc supply pin of 949.

Which supply pin are these DDC input levels referenced to?

Thanks,

Alan

0 Charley Cai over 5 years ago in reply to Alan O

TI__Genius 12866 points

Hi Alan,

Vdd,ddc should be the pull up voltage used for the DDC pin.

Best Regard,s

Charley Cai

0 Alan O over 5 years ago in reply to Charley Cai

TI__Mastermind 32575 points

Hi Charley,

Usually input buffer thresholds are referenced to a device supply pin directly (like VDDIO) or some internally-generated bias.

The customer's SoC uses 3.3V for DDC pullup voltage (not 5V), but I don't see where this pullup voltage would be supplied to 949A.

How does the DDC input low threshold (DDC VIL max = 0.3 x Vdd,ddc) vary with the DDC input's pullup voltage, while the DDC input high threshold (DDC VIH min = 2.7V) stays independent?

Are DDC input thresholds referenced to the RX_5V input voltage, or generated from an internally-regulated voltage reference?

Regards,
Alan

0 Charley Cai over 5 years ago in reply to Alan O

TI__Genius 12866 points

Hi Alan,

I am checking on this and will get back to you.

Best Regards,

Charley Cai

0 Charley Cai over 5 years ago in reply to Alan O

TI__Genius 12866 points

Hi Alan,

The VVIH spec is based on 5V reference.

The fixed 2.7V VIH is correct. If 3.3V pull up is used, the customer need to make sure their VOH min doesn’t dip below 2.7V once reached 949.

Best Regards,

Charley Cai

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DS90UB949-Q1: HDMI control signals - is 3.3V operation possible?