DS90UB935-Q1: Clock output anomaly

Hello Sam,

have you followed this document?

http://www.ti.com/lit/an/snla270a/snla270a.pdf

As you can see in page 6, the required value of CLK_DIV for this mode should be = 1.

Remember also in DVP mode the CSI-2 throughput must exactly match the output throughput: in RAW10: CSI-2 Throughput = CLKIN × 20

Hello Hamzeh,

Thank you for your timely response.

I should clarify that by saying "I set CLK_DIV to 4, M to 1, and N to 14", I was referring to HS_CLK_DIV as CLK_DIV. I just checked and confirmed that CLKIN_DIV is indeed 1, as per the datasheet. 

As for the CSI-2 throughput, the bit rate should be 800 Mb/s, which is 20x the 40 MHz serializer reference clock. 

Edited to add a test result: I've noticed that the PCLK output on the deserializer is stuck at 24.5 MHz, no matter what the timing settings are on the serializer. (When the serializer is unplugged or powered down the PCLK line on the deserializer end is low.) Whereas the serializer datasheet claims that downstream PCLKs will be equal to twice the sensor's reference clock, that is not the case for my system at the moment. Does this imply that the SerDes connection is faulty?

What other factors could affect the forward channel data rate? Page 21 of the DS90UB935-Q1 asserts that the FC data rate is f x 28, but I am still getting f x 16.8 for all cases. Could the error trace back to deserializer settings, or is it isolated to the serializer? 

Thanks ,

Sam

Hamzeh,

Upon closer review of the "Backwards Compatibility Modes" document you reference above, I've realized that Table 2 (Strap Configuration Mode Select) states backward compatibility only works for Coax cable. My system has been designed for STP cable.

Is there any way to use the DS90UB935-Q1 serializer with the DS90UB934-Q1 deserializer in STP RAW10 mode?

Please do let me know if you have a solution or if you can confirm that this will not work.

Edited to add a test result: I decided to go ahead and alter my board for Coax mode functionality (cutting the DOUT- line and terminating both ends to ground w/ RC network as per the data sheet). Conclusion: nothing changed in terms of clocking; the aforementioned issue persists. Nonetheless, the system is now configured for DVP RAW10 over Coax. Any further advice would be much appreciated.

Thanks,

Sam

Here are the results of my measurements on various clocking schemes. The FC value is calculated based on the aforementioned equation, all others were either inputted or measured.

So to clarify, the two questions at hand are:

1) Why is the forward channel data rate so consistently misbehaving?
2) Is it possible to operate the 935/934 link in DVP (backwards compatible) mode over STP cable?

Hello Samuel,

I believe you have some incorrect settings on your system. It can be hardware or register settings. Hence please send me both schematics + register dumps from both devices.

Hamzeh,

I've attached the SerDes register dump and schematics for the circuits that use the SerDes components. I can send you the full schematics via direct message when you add me.

Please do let me know if you spot any errors or need further information. I am looking forward to hearing back from you.

Best regards,
Sam Shafer

3884.Eureka SerDes reg dump.pdf

1881.Eureka SerDes reg dump.xlsx

Hello Sam,

Here is the schematics review feedback. I will check the register dumps and come back to you.

934:
- At CMLOUTs you do have a short circuit. Please connect via 100nF capacitors as per d/s figure 25.
- On the pins 3, 20, 34, you are missing the 10nF capacitors. (See d/s figure 25)
- On pin 17, a 1uF capacitor is missing before connecting VDD18 to IDx and MODE. (See d/s figure 25)
==================

935:
- on PDB pin you need 10Kohm instead of the 12.1Kohm (See d/s figure 18)
- PDB pin must be connected to the main 1V8 not to VDDPLL (See d/s figure 18)
- Mode pin must be connected to the main 1V8 not to VDDD (See d/s figure 18)