Dear team,
Our customer wants to use XIO2001 (PCIe to PCI bridge), then the PCI signals will be connected to CPLD controller and STT-MRAM.
And they ask will they encounter memory cycle problems??
Would you please help to answer it?? Thank you.
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Dear team,
Our customer wants to use XIO2001 (PCIe to PCI bridge), then the PCI signals will be connected to CPLD controller and STT-MRAM.
And they ask will they encounter memory cycle problems??
Would you please help to answer it?? Thank you.
Hi CK,
I have searched for any references to memory cycle issues and I do not see anything in the device files.
However, the question of a "memory cycle problem" is a little vague to me. Do you have more details on this potential issue?
Regards,
Lee