SN65DSI84: PLL_UNLOCK problem

Ville Keskilohko

Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER, SN65DSI85

Hi,

We have designed a new board based on Rockchip RK3399 that has MIPI DSI display interfaces. We are using two SN65DSI84 chips to interface the CPU to two LVDS displays.

We have now struggled getting the bridge to work. Last week we were able to output test pattern although the initialization sequence was not correct. Now when we have fixed the initialization, the PLL_UNLOCK bit is set and it won't clear suggesting a problem with clock. We can't even get the test pattern anymore despite the sequence is now according to specification. However, as the PLL was locking last week with the same board with wrong initialization, we are a bit puzzled.

We know that the initialization might cause odd problems, but correct sequence has been confirmed with oscilloscope, see attachment.

SOFT_RESET, CSR register readback, error clearing and checking is done about 200ms after the initial register setting, not shown on the screenshot.

Is there anything else that can cause PLL_UNLOCK? Some unspecified timing related to DSI clock and enable or something? The DSI clock frequency is 216MHz, LVDS clock divider 3 (72MHz LVDS clock). Corresponding clock registers have been set correctly and as mentioned, was already working with test pattern, but not anymore.

We are out of ideas now except for testing with external REFCLK, but as mentioned, DSI clock should be ok as it has been working...

over 5 years ago

0 Ikechukwu Anyiam over 5 years ago

TI__Mastermind 35130 points

Hi Ville,

The initialization still does not look correct as it looks like the DSI Data has been transitioned to HS before the registers have been configured. The DSI data lanes must remain in LP-11 until after the registers have been configured.

However, the test pattern should still be working in this case since it does not use any input from the DSI data. Can you provide a register dump of the DSI84?

Regards,

I.K.

0 Ville Keskilohko over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 210 points

Hi,

It's not clear from the datasheet that datalines must stay at LP11 during the configuration. There's a note: "If the DSI video stream starts before the device is configured, some of the error status bits
may be set. It is recommended to start streaming after the device is correctly configured as recommended in the initialization sequence in the Initialization Sequence section." It seems to be only recommendation so that error bits will not be set...

We'll try to figure a way to get the RK3399 to keep the datalines at LP11 as long as we wish. So far, we haven't found a way to force the LP11 state in the bus. We'll need to dig deeper into Linux drivers to understand how it can be done. Has anybody in this forum done this with RK3399? Any pointers would be appreciated

BR,

/ Ville

0 Ikechukwu Anyiam over 5 years ago in reply to Ville Keskilohko

TI__Mastermind 35130 points

Hi Ville,

Step 2 in the initialization sequence table reads "After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state".

I haven't seen specific questions about RK3399. It may be best to post this question to the Linux forums to see if any experts there have any insight on how it can be done.

Regards,

I.K.

0 Ville Keskilohko over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 210 points

Hi,

It seems to be a bit tricky to force RK3399 datalines to LP11 although this should be the default state after initializing the CPU MIPI peripheral.

As for the register dump, please find the attachment. There's first the register and after that the value.The only difference to DSI Tuner values are the Video registers, which should have effect only when test pattern generation is enabled.

/ Ville

Fullscreen regvalues.txt Download

    { 0x09, 0x00 },
    { 0x0a, 0x05 },
    { 0x0b, 0x10 },
    { 0x10, 0x26 },
    { 0x11, 0x00 },
    { 0x12, 0x2b },
    { 0x13, 0x00 },
    { 0x18, 0x78 },
    { 0x19, 0x00 },
    { 0x1a, 0x03 },
    { 0x1b, 0x00 },
    { 0x20, 0x00 },
    { 0x21, 0x05 },
    { 0x22, 0x00 },
    { 0x23, 0x00 },
    { 0x24, 0x20 },
    { 0x25, 0x03 },
    { 0x26, 0x00 },
    { 0x27, 0x00 },
    { 0x28, 0x21 },
    { 0x29, 0x00 },
    { 0x2a, 0x00 },
    { 0x2b, 0x00 },
    { 0x2c, 0x20 },
    { 0x2d, 0x00 },
    { 0x2e, 0x00 },
    { 0x2f, 0x00 },
    { 0x30, 0x06 },
    { 0x31, 0x00 },
    { 0x32, 0x00 },
    { 0x33, 0x00 },
    { 0x34, 0x30 },
    { 0x35, 0x00 },
    { 0x36, 0x0f },
    { 0x37, 0x00 },
    { 0x38, 0x50 },
    { 0x39, 0x00 },
    { 0x3a, 0x02 },
    { 0x3b, 0x00 },
    { 0x3c, 0x00 }

0 Ikechukwu Anyiam over 5 years ago in reply to Ville Keskilohko

TI__Mastermind 35130 points

Hi Ville,

Understood, please let me know if you need more support with the DSI84 configuration.

Regards,

I.K.

0 Ikechukwu Anyiam over 5 years ago in reply to Ikechukwu Anyiam

TI__Mastermind 35130 points

Hi Ville,

Please disregard my last reply. I thought I was responding to a different DSI84 post. I will take a look at your register dump now.

Regards,

I.K.

0 Ikechukwu Anyiam over 5 years ago in reply to Ikechukwu Anyiam

TI__Mastermind 35130 points

Hi Ville,

Your dump is missing some registers. Please provide a dump of all of the DSI84 registers.

Although, register 0x0A has a value of 0x05, which indicates that the PLL is not enabled. Are you enabling the PLL (0x0D) in accordance with the initialization sequence?

Regards,

I.K.

0 Ville Keskilohko over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 210 points

Hi,

The register list is what we are writing to the chip, not the readback, which is why there's no status registers. Obviously, we are enabling PLL separately. In initialization CSR registers are first written after which the PLL is enabled. 0x0D is missing from the list, because it's written in separate place.

One note though: DSI Tuner outputs two additional register settings, 0x3D and 0x3E, but they are not documented in datasheet.

We know that the data lines are not in LP11 when they should. Yesterday, we somehow managed to get the image twice on the display so we are assuming the register writes etc. are correct. This sounds more of a timing problem.

BR,

/ Ville

0 Ikechukwu Anyiam over 5 years ago in reply to Ville Keskilohko

TI__Mastermind 35130 points

Hi Ville,

What you're writing to the chip is useful but an actual dump of the device registers would be more useful so that I can see what's actually been written to the DSI84, as well as inspect the status registers. Can you also send me the .dsi output file from the DSI-Tuner? This will be easier to look at it.

0x3D and 0x3E are registers for the SN65DSI85; they are not available for the SN65DSI84.

This does seem to be a timing issue, but I'm still wondering why you're no longer able to successfully display the test pattern. For the test pattern, only the first 7 steps are really relevant, and the DSI DATA lanes being in LP11 shouldn't matter as the DSI data inputs on the DIS84 are in a high impedance state in test pattern mode. Something else must have changed aside from experimenting with the initialization sequence.

Regards,

I.K.

0 Ville Keskilohko over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 210 points

Hi,

Now we found a way to keep the datalines in LP11 and clock running during initialization.

The image is not still visible in the display so there could be some parameter still wrong.

Attached is also a register value dump 0x00-0xff although they are not all used. DSI tuner file also attached in zip as this conversation does not accept .dsi files.

BR,

/ Ville

Fullscreen regval.txt Download

[   10.185775] regval (0x0, 0x35)
[   10.185896] regval (0x1, 0x38)
[   10.186017] regval (0x2, 0x49)
[   10.186137] regval (0x3, 0x53)
[   10.186258] regval (0x4, 0x44)
[   10.186378] regval (0x5, 0x20)
[   10.186499] regval (0x6, 0x20)
[   10.186619] regval (0x7, 0x20)
[   10.186741] regval (0x8, 0x1)
[   10.186861] regval (0x9, 0x0)
[   10.186982] regval (0xa, 0x85)
[   10.187102] regval (0xb, 0x10)
[   10.187223] regval (0xc, 0x0)
[   10.187344] regval (0xd, 0x1)
[   10.187464] regval (0xe, 0x0)
[   10.187585] regval (0xf, 0x0)
[   10.187706] regval (0x10, 0x26)
[   10.187826] regval (0x11, 0x0)
[   10.187947] regval (0x12, 0x2b)
[   10.188068] regval (0x13, 0x0)
[   10.188188] regval (0x14, 0x0)
[   10.188309] regval (0x15, 0x0)
[   10.188430] regval (0x16, 0x0)
[   10.188550] regval (0x17, 0x0)
[   10.188671] regval (0x18, 0x78)
[   10.188792] regval (0x19, 0x0)
[   10.188912] regval (0x1a, 0x3)
[   10.189033] regval (0x1b, 0x0)
[   10.189153] regval (0x1c, 0x0)
[   10.189274] regval (0x1d, 0x0)
[   10.189394] regval (0x1e, 0x0)
[   10.189515] regval (0x1f, 0x0)
[   10.189635] regval (0x20, 0x0)
[   10.189757] regval (0x21, 0x5)
[   10.189877] regval (0x22, 0x0)
[   10.189998] regval (0x23, 0x0)
[   10.190118] regval (0x24, 0x0)
[   10.190239] regval (0x25, 0x0)
[   10.190359] regval (0x26, 0x0)
[   10.190480] regval (0x27, 0x0)
[   10.190600] regval (0x28, 0x21)
[   10.190722] regval (0x29, 0x0)
[   10.190843] regval (0x2a, 0x0)
[   10.190963] regval (0x2b, 0x0)
[   10.191084] regval (0x2c, 0x20)
[   10.191204] regval (0x2d, 0x0)
[   10.191325] regval (0x2e, 0x0)
[   10.191445] regval (0x2f, 0x0)
[   10.191566] regval (0x30, 0x6)
[   10.191687] regval (0x31, 0x0)
[   10.191808] regval (0x32, 0x0)
[   10.191928] regval (0x33, 0x0)
[   10.192049] regval (0x34, 0x30)
[   10.192170] regval (0x35, 0x0)
[   10.192290] regval (0x36, 0x0)
[   10.192411] regval (0x37, 0x0)
[   10.192531] regval (0x38, 0x0)
[   10.192655] regval (0x39, 0x0)
[   10.192775] regval (0x3a, 0x2)
[   10.192896] regval (0x3b, 0x0)
[   10.193017] regval (0x3c, 0x0)
[   10.193137] regval (0x3d, 0x0)
[   10.193258] regval (0x3e, 0x0)
[   10.193378] regval (0x3f, 0x0)
[   10.193498] regval (0x40, 0x0)
[   10.193619] regval (0x41, 0x0)
[   10.193740] regval (0x42, 0x0)
[   10.193861] regval (0x43, 0x0)
[   10.193981] regval (0x44, 0x0)
[   10.194102] regval (0x45, 0x0)
[   10.194223] regval (0x46, 0x0)
[   10.194343] regval (0x47, 0x0)
[   10.194464] regval (0x48, 0x0)
[   10.194584] regval (0x49, 0x0)
[   10.194706] regval (0x4a, 0x0)
[   10.194826] regval (0x4b, 0x0)
[   10.194947] regval (0x4c, 0x0)
[   10.195067] regval (0x4d, 0x0)
[   10.195188] regval (0x4e, 0x0)
[   10.195308] regval (0x4f, 0x0)
[   10.195429] regval (0x50, 0x0)
[   10.195549] regval (0x51, 0x0)
[   10.195670] regval (0x52, 0x0)
[   10.195792] regval (0x53, 0x0)
[   10.195912] regval (0x54, 0x0)
[   10.196032] regval (0x55, 0x0)
[   10.196153] regval (0x56, 0x0)
[   10.196273] regval (0x57, 0x0)
[   10.196394] regval (0x58, 0x0)
[   10.196514] regval (0x59, 0x0)
[   10.196635] regval (0x5a, 0x0)
[   10.196756] regval (0x5b, 0x0)
[   10.196877] regval (0x5c, 0x0)
[   10.196997] regval (0x5d, 0x0)
[   10.197117] regval (0x5e, 0x0)
[   10.197238] regval (0x5f, 0x0)
[   10.197358] regval (0x60, 0x0)
[   10.197479] regval (0x61, 0x0)
[   10.197600] regval (0x62, 0x0)
[   10.197721] regval (0x63, 0x0)
[   10.197841] regval (0x64, 0x0)
[   10.197962] regval (0x65, 0x0)
[   10.198083] regval (0x66, 0x0)
[   10.198203] regval (0x67, 0x0)
[   10.198323] regval (0x68, 0x0)
[   10.198444] regval (0x69, 0x0)
[   10.198564] regval (0x6a, 0x0)
[   10.198685] regval (0x6b, 0x0)
[   10.198806] regval (0x6c, 0x0)
[   10.198927] regval (0x6d, 0x0)
[   10.199047] regval (0x6e, 0x0)
[   10.199168] regval (0x6f, 0x0)
[   10.199288] regval (0x70, 0x0)
[   10.199408] regval (0x71, 0x0)
[   10.199529] regval (0x72, 0x0)
[   10.199653] regval (0x73, 0x0)
[   10.199774] regval (0x74, 0x0)
[   10.199895] regval (0x75, 0x0)
[   10.200015] regval (0x76, 0x0)
[   10.200136] regval (0x77, 0x0)
[   10.200256] regval (0x78, 0x0)
[   10.200377] regval (0x79, 0x0)
[   10.200497] regval (0x7a, 0x0)
[   10.200618] regval (0x7b, 0x0)
[   10.200739] regval (0x7c, 0x0)
[   10.200860] regval (0x7d, 0x0)
[   10.200980] regval (0x7e, 0x0)
[   10.201101] regval (0x7f, 0x0)
[   10.201221] regval (0x80, 0x0)
[   10.201342] regval (0x81, 0x0)
[   10.201462] regval (0x82, 0x0)
[   10.201583] regval (0x83, 0x0)
[   10.201704] regval (0x84, 0x0)
[   10.201825] regval (0x85, 0x0)
[   10.201945] regval (0x86, 0x0)
[   10.202066] regval (0x87, 0x0)
[   10.202187] regval (0x88, 0x0)
[   10.202307] regval (0x89, 0x0)
[   10.202428] regval (0x8a, 0x0)
[   10.202548] regval (0x8b, 0x0)
[   10.202670] regval (0x8c, 0x0)
[   10.202794] regval (0x8d, 0x0)
[   10.202914] regval (0x8e, 0x0)
[   10.203035] regval (0x8f, 0x0)
[   10.203155] regval (0x90, 0x0)
[   10.203276] regval (0x91, 0x0)
[   10.203396] regval (0x92, 0x0)
[   10.203517] regval (0x93, 0x0)
[   10.203637] regval (0x94, 0x0)
[   10.203759] regval (0x95, 0x0)
[   10.203879] regval (0x96, 0x0)
[   10.204000] regval (0x97, 0x0)
[   10.204120] regval (0x98, 0x0)
[   10.204241] regval (0x99, 0x0)
[   10.204361] regval (0x9a, 0x0)
[   10.204482] regval (0x9b, 0x0)
[   10.204602] regval (0x9c, 0x0)
[   10.204724] regval (0x9d, 0x0)
[   10.204845] regval (0x9e, 0x0)
[   10.204965] regval (0x9f, 0x0)
[   10.205086] regval (0xa0, 0x0)
[   10.205207] regval (0xa1, 0x0)
[   10.205327] regval (0xa2, 0x0)
[   10.205447] regval (0xa3, 0x0)
[   10.205568] regval (0xa4, 0x0)
[   10.205689] regval (0xa5, 0x0)
[   10.205810] regval (0xa6, 0x0)
[   10.205931] regval (0xa7, 0x0)
[   10.206051] regval (0xa8, 0x0)
[   10.206172] regval (0xa9, 0x0)
[   10.206292] regval (0xaa, 0x0)
[   10.206413] regval (0xab, 0x0)
[   10.206533] regval (0xac, 0x0)
[   10.206655] regval (0xad, 0x0)
[   10.206776] regval (0xae, 0x0)
[   10.206896] regval (0xaf, 0x0)
[   10.207017] regval (0xb0, 0x0)
[   10.207137] regval (0xb1, 0x0)
[   10.207258] regval (0xb2, 0x0)
[   10.207379] regval (0xb3, 0x0)
[   10.207499] regval (0xb4, 0x0)
[   10.207620] regval (0xb5, 0x0)
[   10.207742] regval (0xb6, 0x0)
[   10.207862] regval (0xb7, 0x0)
[   10.207983] regval (0xb8, 0x0)
[   10.208103] regval (0xb9, 0x0)
[   10.208224] regval (0xba, 0x0)
[   10.208345] regval (0xbb, 0x0)
[   10.208465] regval (0xbc, 0x0)
[   10.208585] regval (0xbd, 0x0)
[   10.208706] regval (0xbe, 0x0)
[   10.208827] regval (0xbf, 0x0)
[   10.208947] regval (0xc0, 0x0)
[   10.209068] regval (0xc1, 0x0)
[   10.209188] regval (0xc2, 0x0)
[   10.209309] regval (0xc3, 0x0)
[   10.209429] regval (0xc4, 0x0)
[   10.209550] regval (0xc5, 0x0)
[   10.209671] regval (0xc6, 0x0)
[   10.209792] regval (0xc7, 0x0)
[   10.209912] regval (0xc8, 0x0)
[   10.210033] regval (0xc9, 0x0)
[   10.210153] regval (0xca, 0x0)
[   10.210274] regval (0xcb, 0x0)
[   10.210394] regval (0xcc, 0x0)
[   10.210515] regval (0xcd, 0x0)
[   10.210635] regval (0xce, 0x0)
[   10.210756] regval (0xcf, 0x0)
[   10.210877] regval (0xd0, 0x0)
[   10.210997] regval (0xd1, 0x0)
[   10.211118] regval (0xd2, 0x0)
[   10.211239] regval (0xd3, 0x0)
[   10.211359] regval (0xd4, 0x0)
[   10.211480] regval (0xd5, 0x0)
[   10.211600] regval (0xd6, 0x0)
[   10.211722] regval (0xd7, 0x0)
[   10.211843] regval (0xd8, 0x0)
[   10.211963] regval (0xd9, 0x0)
[   10.212083] regval (0xda, 0x0)
[   10.212204] regval (0xdb, 0x0)
[   10.212325] regval (0xdc, 0x0)
[   10.212445] regval (0xdd, 0x0)
[   10.212566] regval (0xde, 0x0)
[   10.212687] regval (0xdf, 0x0)
[   10.212807] regval (0xe0, 0x0)
[   10.212928] regval (0xe1, 0x0)
[   10.213048] regval (0xe2, 0x0)
[   10.213169] regval (0xe3, 0x0)
[   10.213289] regval (0xe4, 0x0)
[   10.213410] regval (0xe5, 0x1)
[   10.213530] regval (0xe6, 0x0)
[   10.213655] regval (0xe7, 0x0)
[   10.213775] regval (0xe8, 0x0)
[   10.213896] regval (0xe9, 0x0)
[   10.214017] regval (0xea, 0x0)
[   10.214137] regval (0xeb, 0x0)
[   10.214258] regval (0xec, 0x0)
[   10.214379] regval (0xed, 0x0)
[   10.214499] regval (0xee, 0x0)
[   10.214619] regval (0xef, 0x0)
[   10.214741] regval (0xf0, 0x0)
[   10.214861] regval (0xf1, 0x0)
[   10.214982] regval (0xf2, 0x0)
[   10.215102] regval (0xf3, 0x0)
[   10.215223] regval (0xf4, 0x40)
[   10.215343] regval (0xf5, 0x0)
[   10.215464] regval (0xf6, 0x0)
[   10.215584] regval (0xf7, 0x80)
[   10.215705] regval (0xf8, 0x0)
[   10.215826] regval (0xf9, 0x0)
[   10.215947] regval (0xfa, 0x0)
[   10.216067] regval (0xfb, 0x0)
[   10.216187] regval (0xfc, 0x0)
[   10.216308] regval (0xfd, 0x0)
[   10.216429] regval (0xfe, 0x0)
[   10.216549] regval (0xff, 0x0)

10_display.zip

0 Ville Keskilohko over 5 years ago in reply to Ville Keskilohko

Prodigy 210 points

Just recently, we found a way to output also the image. Therefore, your assistance is no longer required. Thank you for the support.

BR,

/ Ville

0 Ikechukwu Anyiam over 5 years ago in reply to Ville Keskilohko

TI__Mastermind 35130 points

Hi Ville,

I'm glad you were able to resolve the issue. Do you mind posting what your solution was for people in the future that may see this thread?

Regards,

I.K.

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SN65DSI84: PLL_UNLOCK problem