Hi team,
I have questions for Reg 0x6D[7:6] CSI_WAIT_FS1 and CSI_WAIT_FS.
Questions:
When should I set this register?
How does the 954 work when this register is set?
We have an issue where the timing of the FS packet and PH do not match between the MIPI signal source imager and the MIPI receiver SoC.
I would be happy if SerDes could adjust the output timing of this FS and PH.
I would like to know if the above register settings allow such FS and PH timing adjustment.
Is it possible to adjust FS and PH timing in 954 or 953?
Best regards