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SN65DSI84: output not stable on LCD

Matteo Silotto
Prodigy 110 points
Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Hi all,

I'm using SN65DSI84 for a 1920x1080p60 MIPI to dual LVDS conversion.

The output image seems ok but it is shown only for a few frames, it is not stable on the LCD. Sometimes it disappears or is only half drawn on the screen.

When I read back the error register (0xE5) after clear, it's always 0x00 (no error flags). We had tried with the bridge test pattern and the output image is stable and correct (there is no problem on LVDS signals integrity).

What could be the cause of this issue?

Please provide your feedback.

Thanks,

Matteo Silotto

  • 0
    TI__Mastermind 35130 points

    Hi Matteo,

    This looks like line time mismatch issue. Did you use the DSI-Tuner to configure the device registers? If so, please provide the .dsi output file (press ctrl+e in the DSI-Tuner window). Please also provide the datasheet of your LCD.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 110 points

    Dear I.K.,

    yes, I used the DSI-Tuner in order to verify if the kernel driver (that it calculate the registers setting from LCD timings on device tree) set the bridge correctly.

    I don't have the .dsi file but I can regenerate it, if necessary.

    The bridge is now configured with these values:

    i2cdump -f -y 0 0x2c

    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 35 38 49 53 44 20 20 20 01 00 85 28 00 01 00 00 58ISD ?.?(.?..
    10: 20 cc 54 00 00 00 00 00 6c 04 02 00 00 00 00 00 ?T.....l??.....
    20: 80 07 00 00 38 04 00 00 20 01 00 00 09 00 00 00 ??..8?.. ?..?...
    30: 04 00 00 00 31 00 04 00 50 00 04 00 00 00 00 00 ?...1.?.P.?.....
    40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 01 7d 00 00 00 81 00 00 00 00 00 00 00 00 00 00 ?}...?..........
    f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00 ....@..?........

    This is the LCD datasheet:

  • 0 in reply to Matteo Silotto
    TI__Mastermind 35130 points

    Hi Matteo,

    Please regenerate the .dsi file; it will be easier for me to look at then the just the register values.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 110 points

    Dear I.K.,

    attached the DSI file.

    Regards,

    Matteo Silotto

    Adelsy_AM-19201080F1TZQW-A0.zip

  • 0 in reply to Matteo Silotto
    TI__Mastermind 35130 points

    Hi Matteo,

    From the settings in your .dsi file this issue is likely due to a line time mismatch. Since you're using the DSI84 in a single to dual configuration, the horizontal parameters from your DSI input need to be double the horizontal parameters on the LVDS output, but right now you have them as 1:1. Think of cutting a display in half vertically. The output of your DSI source should be programmed for the entire display, but since the DSI84 has dual outputs, each output will be programmed horizontally for one half of the display. 

    I'm attaching a .dsi file with new settings that you can try. You can import them into the DSI-Tuner tool and then generate the text file with the register settings:

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/Matteo.dsi

    Please also make sure that the output from your DSI source matches the new DSI input settings of this file.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 110 points

    Dear I.K.,

    analyzing your .dsi file we get some useful information regarding the setting of H-sync registers.

    With some other fixies on the H-sync registers setting (increased bporch, reduced fporch), we have got an improvement in LCD image stability but the issue isn't completely solved.

    Sometimes we see a wrong frame, please see the attached video:

    Also now we get a CHA_SYNCH_ERR from error register:

    i2cset -f -y 0 0x2c 0xe5 0xff     (to clear pending errors)

    i2cget -f -y 0 0x2c 0xe5
    0x80

    Could this explain the frame issue? What can cause a CHA_SYNCH_ERR error?

    Thanks and best regards,


    Matteo Silotto

  • 0 in reply to Matteo Silotto
    TI__Mastermind 35130 points

    Hi Matteo,

    That error is typically caused by a line time mismatch between the DSI side and the LVDS side. Have you checked that your DSI source is outputting the exact video timing values (active pixels, blanking pixels, DSI clock frequency) that you programmed into the DSI84? The DSI84 doesn't realign timing.

    Regards,

    I.K.