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DS250DF230: daisy-chained fashioned calibration clock

K.Yaita
Guru 29720 points
Part Number: DS250DF230

Hi Team,

My customer considers using three DS250DF230s with daisy-chained fashioned calibration clock (connects CAL_CLK_OUT to next CAL_CLK_IN) as datasheet Figure 18.

1)
Is there any layout guidelines to use daisy-chained fashioned calibration clock?
I believe it is required to prevent reflection.

2)
Could you tell me output impedance(Ω) for CAL_CLK_OUT? 

Best Regards,
Yaita

  • 0
    TI__Guru* 93670 points

    Hi Yaita,

    CAL_CLK_IN and CAL_CLK_OUT are 2.5V LVCMOS input and output. Like other LVCMOS signals these are not impedance controlled. Please check data sheet with respect to duty cycle, ppm, and input/output threshold levels. This clock is used for reference to enable device for initial lock acquisition only and are not in high speed signal path.

    Regards,, Nasser

  • 0 in reply to Nasser Mohammadi
    Guru 29720 points

    Nasser-san,

    Thank you for your feedback.

    My customer is designing PCB layout now, and wants to be free from clock reflection trouble.
    So, considers utilizing the source impedance matching technique which absorbs the reflected signal on driver side by making driver source impedance as same as the trace impedance.
    To realize it we need to know the source impedance of CAL_CLK_OUT pin.
    Can you provide me the source impedance of this pin?

    Another question is that, if trace length is short enough we do not need concerning reflection problem.
    How much trace length we can use without concerning reflection?

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Guru* 93670 points

    Hi Yaita-San,

    Source impedance is high like a typical LVCMOS logic. I suggest we should use rise/fall time to estimate trace length without worring about the reflections.

    Rise/fall time is expected to be in order of 4ns with a typical load of 33pF capacitance. Please try to keep trace length less than 4 inches.

    Regards,, Nasser