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DP83TC811S-Q1: Packet loss issues

Tharindu Silva
Prodigy 60 points

Part Number: DP83TC811S-Q1
Other Parts Discussed in Thread: DP83TC811EVM, DP83822I, , DP83TC811

Hello,

I am using the DP83TC811S-Q1 in a purely physical ethernet to automotive ethernet media conversion application. I followed the reference design for the 811 chip (DP83TC811EVM) and decided to use RGMII with the DP83822I ethernet PHY. Prior to implementing the design, I tested the EVM by using 2 in a back-to-back configuration (PC1 <-> EVM <-> EVM <-> PC2) and I used iperf3 to monitor packet loss. In this scenario, the EVM worked fine and I recorded near 100Mbps with 0% loss. After designing the media converter and getting the boards, I tried a similar test (PC1 <-> my converter <-> EVM <-> PC2) using iperf3 and I recorded around 1.2% loss going from PC1 to PC2, and 0% loss going from PC2 to PC1. I don't believe there are any issues with the EVM as I had tested it beforehand, so I'm thinking that there might be an issue with the transmitter in the 811, or the receiver in the 822 on my board. I used 2.49k pull-up resistors on the Rx_D1 and Rx_D2 pins so that MAC[2:0] = 110 to get the 811 PHY into RGMII with internal Tx and Rx delay mode. On the 822 chip, I used a 13k pull-up and 2k pull-down on the CRS pin to get it into mode 2, and a 6.19k pull-up and 2k pull-down on the Rx_ER pin to get it into mode 3.

Are there any issues with this configuration? I figured these were the same pull-ups/-downs populated on the EVM board as well.

Thanks,

Tharindu

  • 0
    TI__Mastermind 18425 points

    Hi Tharindu,

    The straps look correct on your board. Have made any changes in the board schematics or layout between the TI EVM and your board?

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 60 points

    Hi Aniruddha,

    I did add the optional lowpass filter that was mentioned in the DP83TC811's datasheet. I also don't have any 0 ohm resistors connected between the RGMII traces. I also used discrete magnetics for the ethernet side instead of an RJ45 jack with integrated magnetics. The discrete magnetics unit was from the recommended list mention in the DP83822I datasheet, so I didn't think this would cause an issue.

    Regards,

    Tharindu

  • 0 in reply to Tharindu Silva
    TI__Mastermind 18425 points

    Hi Tharindu,

    Would you be able to share the schematics of your custom board?

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 60 points

    I have asked an FAE to forward you the schematic.

    Regards,

    Tharindu

  • 0 in reply to Tharindu Silva
    TI__Mastermind 18425 points

    Hi Tharindu,

    Thank you for  sending the schematics over. Largely the schematics looks correct, but I would like to make some suggestions. 

    1. MDC looks like it is No Connect. Is there access to that pin at all? It will not affect normal operation but I wanted to check if there is an option to access the registers.

    2. I see that the crystal that you are using is different than the crystal used on the 811 media converter evm. However the load capacitors on the crystals on your board are same as the evm. Load capacitors need to be adjusted based on the crystal. The crystal on your board is a 18pF crystal which would need 33pF capacitors on XI and XO. Can you make this change for both DP83TC811 and DP83822 and try again?

    3. If step 2 does not work, can you try to remove the ESD protection diodes and try again? First remove the ESD protection diodes on DP83TC811 and see if shows improvement in packet error.

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 60 points

    Hi Aniruddha,

    Thanks for the suggestions. Unfortunately, increasing the load capacitance actually increased the packet loss to around 5%. Also, removing the ESD protection made no difference.

    I was able to solder some wires to the MDC and MDIO pins and accessed the registers of each PHY using TI's EVM. I included some of the register values for each PHY below. I didn't notice anything unexpected, but if you could take a look at the values and confirm it would be greatly appreciated.

    DP83TC811:

    Register 0000 is: 2100

    Register 0001 is: 0065

    Register 0002 is: 2000

    Register 0003 is: A253

    Register 0009 is: 2000

    Register 000D is: 401F

    Register 000E is: 0000

    Register 0011 is: 010B

    Register 0012 is: 0000

    Register 0013 is: 4000

    Register 0014 is: 0000

    Register 0015 is: 0000

    Register 0016 is: 0100

    Register 0017 is: 5A49

    Register 0018 is: 0010

    Register 001F is: 0000

    Register 0467 is: 003C


    DP83822:

    Register 0000 is: 3100

    Register 0001 is: 786D

    Register 0002 is: 2000

    Register 0003 is: A240

    Register 0004 is: 01E1

    Register 0005 is: CDE1

    Register 0006 is: 000D

    Register 0007 is: 2001

    Register 0008 is: 44F5

    Register 0009 is: 0000

    Register 000A is: 0100

    Register 000B is: 1000

    Register 000D is: 401F

    Register 000E is: 0000

    Register 000F is: 0000

    Register 0010 is: 0615

    Register 0011 is: 0108

    Register 0012 is: 0000

    Register 0013 is: 0000

    Register 0014 is: 0000

    Register 0015 is: 0000

    Register 0016 is: 0100

    Register 0017 is: 0249

    Register 0018 is: 0400

    Register 0019 is: 8C01

    Register 001A is: 0000

    Register 001F is: 0000

    Register 0467 is: 0E4F

    Thanks,

    Tharindu

  • 0 in reply to Tharindu Silva
    TI__Mastermind 18425 points

    Hi Tharindu,

    Comparing the register 0x17 of both devices I see that on 811 both RGMII RX and TX delays are on. And on DP83822, only TX delay is on and RX is off. TX of 822 is connected to RX of 811. Since 811 RX also has the internal delay enabled what might be happening is that the delays are adding up in both the devices and its throwing off the timing requirement. Can you disable the TX delay in DP83822 by writing to register 0x17[11]. Please note the change in the description for register 0x17[11] of DP83822. '1' will disable the TX delay and '0' will enable the TX delay (it's currently '0' as per your register dump above).

    -Regards

    Aniruddha