DP83848I: No link, stuck during Auto-MDIX

Hi Florian,

Are you changing any registers on the PHY via software or straps? Have you checked the link with another DP83848?

-Regards

Aniruddha

Hi Aniruddha,

thanks for you reply, All of the strapping pins have external pullups or pulldowns. Their setting - pullup or pulldown - corresponds to the default strapping (internal pullups/pulldowns) from the datasheet.

The registers are also changed via software to their defaults after every power cycle. Maybe this is a little bit to much of redundancy. But it shouldn't do any harm it think.

I can reproduce this error with others of our interface electronics containing the DP83848. Or did you mean I should connect two DP83848 together? Well, I did this anyway. The result is: sometimes a 100 Mbit Full-Duplex link is established like it should. But sometimes only a Half-Duplex link can be established. I looked at the registers but didn't really understand what happens. Maybe you have any ideas.

Registers after power up:

PHY registers:
BMCR: 0x3100
BMSR: 0x7849
ANAR: 0x01E1
ANLPAR: 0x0000
ANER: 0x0004
ANNPTR: 0x2001
PHYSTS: 0x0000
MICR: 0x0000
MISR: 0x0000
FCSCR: 0x0000
RECR: 0x0000
PCSR: 0x0100
RBR: 0x0021
LEDCR: 0x0000
PHYCR: 0x8021
10BTSCR: 0x0904
CDCTRL1: 0x0000
EDCR: 0x6011
AUTO-NEGOTIATION: BMCR: 0x1000 / ANAR:0x01E1

Connecting two DP83848 together, success, 100 Mbit Full-Duplex:

>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4100 / ANLPAR:0x41E1 // PHYCR:0x8021 $
>BMSR:0x7869 / PHYSTS:0x4115 / ANLPAR:0x41E1 // PHYCR:0x8021 $
#-X-#: AN Done, Result=3 / 27
>successful<
100 Mbps, Full Duplex

Connecting two DP83848 together, failure, 100 Mbit Half-Duplex:

>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0000 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0100 / ANLPAR:0x41E1 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $  => False Carrier event has occurred since last read of FCSCR??
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x0900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4900 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4D00 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4D00 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7849 / PHYSTS:0x4D00 / ANLPAR:0x0000 // PHYCR:0x8021 $
>BMSR:0x7869 / PHYSTS:0x4D11 / ANLPAR:0x0081 // PHYCR:0x8021 $
#-X-#: AN Done, Result=3 / 25
>Not supported by Link Partner<
Settings used: Examined Speed / Half Duplex (default)
100 Mbps, Half Duplex

Regards,

Florian

Hi Florian,

Can you share the schematics of the board? The power up register settings of the PHY seem ok.

-Regards

Aniruddha

Hi Aniruddha,

can I send you the schematics via private message?

Regards,

Florian

Hi Florian,

Yes, private message on E2E is should be fine. We also have a app note to check the schematics for DP83848: 

You can also in parallel check the schematics while I am reviewing it.

-Regards

Aniruddha

Hi Aniruddha,

sorry for spamming the forum. But I think you have to accept my friendship request before I can send you a private message.

Meanwhile I'll work through the app note.

Regards,

Florian

Hi Florian,

Apologies for the delay, there was some mix-up in thread tracking and this thread got dropped off from my list of active questions. I have accepted your connect request on E2E so you should be able to send confidential material over to me via private chat. I also have your schematics and have some questions about it.

Is RBIAS resistor 1% tolerance?

Are the 49.9 ohm resistors 1% tolerance?

Does the 50MHz clock meet the datasheet requirement?

Does the magnetics meet the datasheet requirement?

Do you perform a hardware reset or power cycle after every link up test?

How long do you wait before you consider link attempt a failure and move to the next iteration?

-Regards

Aniruddha

Hi Aniruddha,

to answer your questions:

• The resistor tolerances are 1%.
• Regarding the 50Mhz clock: it seems that the jitter requirements aren't met. I'm going to test with an oscillator with tighter jitter specs and report back.
• We use one of the recommended magnetics from the app note (J0011D21BNL).
• I did the link up test in different ways:
  • power cycles between consecutive tests
  • just disconnecting and reconnecting the ethernet cable
  • initiating a software reset via Masic Mode Control Register
  • The success rate of getting a link is independent from the approach it take.
• I consider the link attemp a failiure after a couple of seconds. In my excperience if it works it takes about 2 s at max. If it doesn't, waiting for even minutes won't result in a link.

Best regards
Florian

Hi Florian,

Thanks for the update. Let me know if improving the clock helps improve the link up. For your link up time, can you also try relaxing your cut-off time to 6-8 seconds when you re-test. There is no max link up defined in the IEEE standard and sometimes normal link up can take 5+ seconds. 

-Regards

Aniruddha

Hi again,

it took me some time to do a test with a different clock. I disconnected the previously used clock (from the FPGA) and used the optional dedicated 50 MHz oscillator on the PCB (also ensured it meets the requirements from the datasheet). It didn't make any difference.

I noticed that it can take pretty long for the link to establish. Sometimes like 20 seconds. But in most cases if the link isn't established within an few seconds it never will.

I still think it has something to do with the AUTO-MDIX feature. The state machine in the PHY stops swapping the pairs when the cable is plugged in:

• Either the PHY 'thinks' the pair's polarity is ok, so no reason to swap them...
• or the state machine get's stuck in a certain state. Are there any registers which could provide insight?

I'm going to measure MDI-signals before and after the magnetics again. Maybe I can find out something that way.

Best Regards,
Florian

Hi,

I think I got to root of the problem. And it's very likely that it isn't the DP83848I.
I had a closer look at the Fast Link Pulses (FLP) during Auto-Negotiation:

• The test PC that I used for all my tests was particulary "good" reproducing the link problem.
• As it turns out, the FLPs that the DP83848I receives from the test PC on it's RX-pair are significantly smaller than compared to those the TX-Pairs (see the picture)
  
• I double checked this by measuring the test PC signals without any link partner physically connected to it.
• Then I used a longer 10 m Ethernet cable for the connection betwenn my DUT and the test PC. As expected this attenuated the FLPs by another few milivolts.
• What was utterly unexpected: the link problem was gone!

My guess what happend:

• The low amplitude FLPs were above the threshold of the DP83848I to detect them (at least partially). Though it did not switch to MDIX
• The low amplitude may have caused receive errors that prevented to establish a proper link
• With the longer cable the FLPs are below the threshold of the DP83848I. Though it only sees FLPs on the TX-pairs, switches to MDIX and everything works fine.

I'm going to look for other PCs or Ethernet switches where the link problem was observed. I will get back an report if I found out anything new.