TPS25740B: Need confirmation on the design and layout

“The team is on CNY off, and response maybe slow. Will get back to you soon”

Hello Felix,

Schematic Review

Ensure USB1_PD_EN_L is between 1.6-2 V. 

C349 is recommended to be a 0.33 uF capacitor

R360 is recommended to be 24.9 ohms.

Connect VDD to ground and the bypass capacitor between VDD and VBUS.

Thanks,

Emma

Hi Emma,

Regarding to the VDD connection - We kept the 3.3V with VDD purposefully, so as to make the PD device functioning even before the VBUS comes in.

In our system 3.3V_Main will be generated first once the external supply connected to the board. 

When its sourcing the VDD of the USB PD device, we can still get the CC communication happens and get the Sink attached signal to the MCU (which is powered by 3.3V_Main) and then the MCU will enable the USB PD. 

Please confirm whether our understanding is correct and let us know whether the circuit would functioning as expected.

Regards,

Felix.

Hi Emma,

Thanks for your input and confirmation on the VDD connection.

One more clarification needed on USB1_PD_EN_L.

As per datasheet, GD\ has internal pull down, by default its Gate drive is OFF. So, we are keeping a Pull up to keep the gate drive on.

Is this implementation holds good? 

This signal is driven by MCU with 3.3V level.

Whats the reason the Min is given as 2V and Max is given as 1.6V in the datasheet for GD\.

Is it due to the active low logic for this pin?

Kindly explain.

Regards,

Felix.

Hi Emma,

Thanks for the response on the layout.

We believe the layout out is proper as per recommendation and there is no more improvement needed.

Regards,

Felix. 

Hi Felix,

GD\ disables the gate driver when it is pulled low so your implementation is good.

The low level input voltage is 1.6V max and the absolute max rating for GD\ is 7V so your input of 3.3V is fine. The pin is active low. 

Thanks,

Emma