DP159RGZEVM: DP159 DDC in snoop mode

Hi Lam,

It looks like the TMDS_CLOCK_RATIO bit is not getting properly set in snoop mode. Have you tried toggling HDP_SNK after you connect the HDMI2.0 source?

Regards,

I.K.

Hello I.K.

HDP works OK.  Above scope captures are the DDC_SDA line.   Top is when DDC interface goes through the DP159 ( source works OK and shows content to display) and bottom is when DDC interface is snooped by DP159  (source is off and no content to display).  

I do not understand why there is a difference in DDC traffic between both connections as I assume the DP159 would not alternate the DDC traffic content, regardless how it taps DDC traffic.  Is it a correct assumption? 

Again, this happens only when I use a PC graphic card to send HDMI 2.0 signal (4K 60Hz).  I do not have issue when I use same graphic card to send out HDMI 1.4b signal (4K 30 Hz).  Also no issue when I use Lecroy QD780E to send 4K 60Hz.   So I guess EDID content is different in both cases and I wonder what is the DP 159 contribution to that difference.

Thanks

Lam

Hi Lam,

To clarify, when you say "HPD works ok" does this mean that when you toggle HDP_SNK in snoop mode, the output is shown properly for HDMI2.0? 

Also, for your Lecroy QD780E source, both DDC configurations correctly output HDMI2.0? 

Can you share the configuration you have (SDA/SCL) for DDC snoop?

Regards,

I.K. 

Hello I.K.,

I suspect timing issue.  Attached are the 2 EDID transactions

1.  the EDID transaction is complete when  the DDC interface is run through DP159 with both blocks read (F22)

2.  the EDID transaction is incomplete when  the DDC interface is snoop by DP159 with only 1st blocks read (F23) and 1st byte of that block is 0xFF instead of 0x00

Questions:

1.  I keep HPDSNK_GATE_EN reg A bit 6 = 0  (0 – HPD_SNK passed through to the HPD_SRC (default)) in both cases, does it matter?

2.  Could you explain more on clock stretching?  Look like there is no clock stretching with DP159 in snoop mode and that might cause issue preventing EDID transaction to complete?

Regarding DDC configuration in snoop mode, I connect DDC_SNK straight between HDMI connector and DP159 pins 33, 38, 39 and then to a 5V-to-3V voltage translator before connecting to FPGA.  All 3 nodes are pulled up 4.7K to 5V from HDMI connector.  DDC_SRC pins 46, 47 are pulled down 4.7K to GND while HPD_SRC left unconnected

Thanks

Lam

Hello I.K.,

Another detail, what I show above is when using a NVidea PC graphic card 

Lecroy QD 780E works OK with both configurations sending 2160p60.  I will capture the EDID transaction for both configurations and compare.

Thanks

Lam

Hi Lam,

Can you change the pullup resistors to 2k? This may help with the timing. 4.7k violates the pull-up resistance requirement of the HDMI specification. In snoop mode, you can also remove the pull-ups on SCL_SNK and SDA_SNK when you connect them to your source as the source will already have 2k pulls-ups.

For your question 1: That is fine, but if you are changing from HDMI1.4b to HDMI2.0 then the HPD_SNK pin needs to be toggled. 

For your question 2: The SCL_SRC and SDA_SRC for the DP159 always has clock stretching regardless of snoop mode. This is why we recommend to bypass these pins if the source does not support clock stretching. 

Also, can you directly connect the DDC from the NVidea card to DDC on your display (completely bypassing the DP159) and see if the EDID transaction is completed (note that for HDMI2.0 you'll need to manually set bit 0 and bit 1 in register 0bBh for the DP159 to adjust the TMDS clock ratio).

Regards,

I.K.