XIO2001: XIO2001 confirmation

1. Both PCIe and PCI buses have three kinds of transactions: configuration register accesses (reads from or writes to a specific register number), I/O accesses (reads from or writes to a specific I/O address), and memory accesses (reads from or writes to a specific memory address). In modern systems, almost all transactions are memory accesses.

The bridge has configuration registers that tell it which address ranges are occupied by downstream devices; the bridge translates all PCIe transactions to such addresses into PCI transactions. Similarly, the bridge translates all upstream PCI transactions into PCIe transactions.

2. The latency timer has nothing to do with "detection".

A PCI bus has a hardware module, the arbiter, which coordinates how multiple devices are allowed to access the bus. All bus master devices have a signal (#REQ) to tell the arbiter that they request access to the bus; they also have a signal (#GNT) by which the arbiter tells them that the bus is free and that the request is granted.

The latency timer has an effect only when there is a conflict between two bus masters. When one bus master is in the middle of a long burst, and a second bus master wants to access the bus, and the arbiter decides that it is now the second bus master's turn, then the #GNT signal to the first bus master is deactivated. At this point, the first bus master is allowed to continue for the number of cycles specified in its latency timer register. Only when the first bus master has stopped the burst will the arbiter activate the #GNT signal to the second bus master.

(Increasing the latency timer usually increases the actual bandwidth because the device is allowed to do longer bursts.)

The Secondary Latency Timer register specifies the latency timer for the XIO2001's own PCI interface.

3. This is correct.

Thank you for your reply, Mr Clemens.
Mr Iwata was asking a question on my behalf

I have an additional question about "detection".

> The latency timer has nothing to do with "detection".

I consider "detection" to be the active time of the #IRDY signal, and I want to ask more about that.
Is there a register that manages the active time (number of clocks) of the #IRDY signal?
Or is there a mechanism to make the #IRDY signal inactive before communication is completed?

Thank you

Thank you

A single PCI transfer is completed in the clock cycle in which both IRDY# and TRDY# are active. This means that the length of the active time of the IRDY# signal is controlled only by the target.

The PCI specification says:

3.5.1.2.   Target Subsequent Latency

Target subsequent latency is the number of clocks from the assertion of IRDY# and TRDY# for one data phase to the assertion of TRDY# or STOP# for the next data phase in a burst transfer.  The target is required to complete a subsequent data phase within eight clocks from the completion of the previous data phase.  This requires the target to complete the data phase either by transferring data (TRDY# asserted), by doing target Disconnect without data (STOP# asserted, TRDY# deasserted), or by doing Target-Abort (STOP# asserted, DEVSEL# deasserted) within the target subsequent latency requirement.

In most designs, the latency to complete a subsequent data phase is known when the device is being designed.  In this case, the target must manipulate TRDY# and STOP# so as to end the transaction (subsequent data phase) upon completion of data phase "N" (where N=1, 2, 3, ...), if incremental latency to data phase "N+1" is greater than eight clocks.  For example, assume a PCI master read from an expansion bus takes a minimum of 15 clocks to complete each data phase.  Applying the rule for N = 1, the incremental latency to data phase 2 is 15 clocks; thus, the target must terminate upon completion of data phase 1 (i.e., a target this slow must break attempted bursts on data phase boundaries).

For designs where the latency to complete a subsequent data phase cannot be determined in advance, the target is allowed to implement a counter that causes the target to assert STOP# before or during the eighth clock if TRDY# is not asserted.  If TRDY# is asserted before the count expires, the counter is reset and the target continues the transaction.

The implication is that a partial transfer will be completed when the latency timer expires. But this is a property of how fast the target can do the transfer, and cannot be controlled with a register.

A master abort happens when no target responds. But that timeout is pretty much constant (see the section "Master Initiated Termination" in the PCI specification).

The MAM bit controls whether the bridge reports master aborts (this is disabled by default for PC compatibility). The MAM bit does not affect if or how fast master aborts happen.