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SN65MLVD040: Bridging LVDS and M-LVDS

Jim M.
Prodigy 50 points
Part Number: SN65MLVD040
Other Parts Discussed in Thread: SN65LVDM176, SN65MLVD206B

Hello, I'm trying to get some guidance on a design I'm working on. Right now I have a Xilinx FPGA driving some LVDS GPIO out of a backplane, to an I/O card, and out the front panel of my system to a second subsystem through a cable (see below image). The signal going out over the cable is to be Type-2 M-LVDS.

Since this design is a prototype, there's a chance that we'd need to change the direction of some of these differential signals going out over the cable. This isn't a big deal on the FPGA since it's just a matter of configuring the I/O buffer primitive. For the I/O card, I like the SN65MLVD040 since that chip provides half-duplexing, which should allow me to change the direction of the M-LVDS pairs by toggling the DE/RE* pins together.

However, I have a few questions about this approach:

  1. Is there any easier way bridge LVDS and M-LVDS?
  1. If possible, I'd like to avoid going through two signal conversions (LVDS <--> LVTTL <--> M-LVDS)

  • If converting to LVTTL is unavoidable, are there any LVDS transceivers with similar functionality to the SN65MLVD040 (specifically with regard to half-duplexing)?
    1. There are no strictly LVDS transceivers like this, but I have found the SN65LVDM176. However, this IC is an 'LVDM' half-duplexing transceiver. From my understanding, LVDM is similar to LVDS except with 2x drive current? Is this compatible with a Xilinx Ultrascale differential I/O buffer? (note that the built-in termination can only be 100 ohms or turned off completely. I cannot add/remove/modify termination on the FPGA board outside of the FPGA).
    2. Would there be any issues driving and/or receiving between a regular LVDS transceiver and an LVDM transceiver?

  • If I do need to convert to LVTTL to get from LVDS to M-LVDS, can I tie the single-ended drive/receive I/O on each chip together and treat them as a single, bi-directional LVTTL line as well (see below diagram)?

Thanks for your time

  • 0
    TI__Mastermind 35130 points

    Hi Jim,

    For your configuration it looks like the LVDS to LVTTL bridge is unavoidable, as we don't have any LVDS-LVDS transceivers. 

    You can find LVDS transceivers similar to the SN65MLVD040 here: http://www.ti.com/interface/lvds-m-lvds-pecl/products.html#p1389=M-LVDS (e.g. the SN65MLVD206B) 

    The SN65LVDM176 device you found can also work here as LVDM is ideal for point-to-point half-duplex applications (see figure 19 in the datasheet). 

    For your question about tying the single-ended drive/receive I/O on each chip together and treating them as a single, bi-directional LVTTL line, I'm not sure if this would work as intended. Signal integrity issues would arise from the stub that's created and the possible additional loading of the driver/receiver. It would be better to just use an LVDS driver and LVDS receiver as an intermediate.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    TI__Mastermind 43795 points

    Hi Jim,

    The only other option would be to use a LVCMOS inputs and outputs to drive the MLVDS transceiver directly.

    In a point to point link LVCMOS should work at "MLVDS" speeds.  What is the datarate?

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Prodigy 50 points

    Lee Sledjeski said:

    In a point to point link LVCMOS should work at "MLVDS" speeds.  What is the datarate?

    We were aiming for a signaling rate of 250 Mbps.

    Also, thank you for your replies, Lee and I.K.

  • 0 in reply to Jim M.
    TI__Mastermind 43795 points

    Hi Jim,

    How about just driving/receiving the cable directly with the FPGA LVDS IO.  At 250 Mbps I'm assuming there is only one transceiver at the other end.

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Prodigy 50 points

    So this cable is going to be running between two subsystems in an environment with some degree of EMI (although I'm not exactly certain how bad this is expected to be). Would LVDS over a ~5m cable be appropriate in this case? I know signal integrity is partially going to be dependent on cabling, shielding, datarate, etc. but also choosing the correct signaling standard is a big factor in it as well.

    If it sounds like LVDS is suitable for this, then I'll go with that, but if there's a better alternative I'm open to suggestions.

    Thanks again for your help,

    -Jim M.

  • 0 in reply to Jim M.
    TI__Mastermind 43795 points

    The a key factor with LVDS and cables is the need for a common ground.  Since the devices are DC coupled the interface can be sensitive to ground shifts etc.

    I think most cables would support the attenuation requirements.

    Regards,

    Lee