CCS/TPS65983B: PD compliance test fail

Hi Paul,

Can you please share the Project file used in your configuration and also the VIF file used for the compliance testing? Such failure analyses take some time. I will update you as early as possible with my findings. 

Regards,
Kedar

Hi Kedar,

Thank you for your quickly reply.

I just want to attach file, but some error happen...

Regards,
Paul

Hi Kedar,

I change these file to zip file.

My bin file: /cfs-file/__key/communityserver-discussions-components-files/138/E3803_5F00_PD_5F00_FW_5F00_20190718.7z

I just follow the TAHINI CREEK VIF: /cfs-file/__key/communityserver-discussions-components-files/138/5736.Tahini_5F00_Creek_5F00_VIF.txt.7z

Regards,
Paul

Hi Kedar,

      Any update? I need to gerber out tomorrow...could you please inform me does the fail impact HW?

      BTW, Ben provide a link to me to put project file as below and he tell me he will guide you how to download. Do you get his information?

https://txn.box.com/s/in9uvs3zt4x9xkox3gin4ljmnyl8t0cx

Hi Paul Chen,

I received the files separately from Ben Kuo. Also, It seems that you are using an older version of the firmware (0000.06.49). The latest version is (0000.06.63) which includes some compliance related issue fixes.

I have requested Ben to share the relevant files with you.

Can you please recreate your project on our latest version of the GUI (v4.13) based on the latest binary, and share the compliance results after running this version?

Also, please share your project file for our review.

Regards,
Kedar

Hi Kedar,

Thank you for your reply.

Do you mean if I use the latest version of GUI(v4.13) to create a new FW, these PD fail will be solved?

If yes, could you also provide the change note and guide me which fail is relate on the change note?

GRL inform me TDA.2.1.2.1 and TD.PD.SRC3.E32 need to be solved, other are known issue. really?

I will upload the layout file for you review, is it enough for you?

/cfs-file/__key/communityserver-discussions-components-files/138/e3803_2D00_0726.7z

Hi Paul,

Some of the issues fixed are for VDM compliance issues. But it would make sense to see if the newer binary would cause you any issues, since that would be the ones we would look at possible fixes.

The link you shared has a board file. Can you please share the project file from the configuration tool?

Regards,
Kedar

Hi Paul,

I looked at the GRL failures. None of the failures seem to be related to hardware. The failures seem to be at a PD protocol level. 

Please allow me some time to analyze and isolate the failures.

Regards,
Kedar

Hi Kedar,

Thanks for your reply.

Sorry for miss-understand, I put the .pjt file as below:

/cfs-file/__key/communityserver-discussions-components-files/138/E3803_5F00_PD_5F00_FW_5F00_20190718.pjt

Is ant document for how to use the tool?

Ex: How is DP HOT Plug signalled? Physical or Virtual?

Hi Kedar,

Thanks for your reply.

1. How many time you need to analysis ?

2. The file I upload is enough for you?

Please let me know if there is any data you need.

Hi Kedar,

May I know which failure will impact the HW?

I postpone my gerber out schedule, but I have to know how many days to delay the schedule!

I know you need some time for analysis......but it should be have a date. I need to inform them to my team and boss.

Could we have a con-call?

Hi Kedar, 

Sorry, I seems misunderstand what you want to say.

Do you mean there is no failure item related on HW and be at PD protocol level, right?

BTW, may I have the GUI(v4.13)? Ben tell me he don't have the GUI.

Hi Paul,

Yes. The failures don't seem to be related to Hardware. I have shared the GUI with Ben. He will be sharing it with you.

Regards,
Kedar

Hi Kedar,

GRL test new PD FW and old failure can be solved but there is a new failure.

The test report and log I already put in TI BOX, and please below my pjt file./cfs-file/__key/communityserver-discussions-components-files/138/PD_5F00_VID_5F00_20200213.pjt

Please kindly help review and tell me which setting should be corrected.

Thanks.

Paul 2/18

Hi Paul,

I will be able to take a look at this and respond sometime next week. Is this OK? 

I hope your gerber release was not blocked, since the earlier failures had nothing to do with hardware.

Regards,
Kedar

Hi Kedar,

Thank you for your reply. I release the gerber once I receive your information. 

There is only 1 fail item (TD.PD.SRC3.E6) and I will get EVT2 PCBA next week, could you try to reply me this week?

Hi Paul,

Sorry, I wasn't able to respond last week, since I was off.

Can you share the failure reports?

Regards,
Kedar

Hi Kedar,

I put report in TI BOX, file name is '0217 PD retest with new FW'.

https://txn.box.com/s/px2bwt80i2m6l91edq0udhky01ba5irc

I already receive the EVT2 PCBA, please help reply asap.

Thank you.

Paul 2/25

Hi Paul,

The test that failed is TDA 2.3.3.1. For your DRP configuration the test that needs to be run is actually TDA 2.3.3.2, since your VIF file says it's a DRP port type.

We are investigating why GRL picks this test instead of TDA 2.3.3.2. We verified on a Lecroy compliance tool that for a DRP configuration, TDA 2.3.3.1 is skipped and TDA 2.3.3.2 is applied, which passed the test.

Please take a look at "PD Communications Engine USB PD Compliance MOI" document, section 3.13.5 and 3.13.6, and look at the field "Applies to" in the field.

Regards,
Kedar

Hi Kedar,

Thank you for your reply.

I think TBT3 docking will not sink PD power from host site, so maybe DRP is not correct setting.

BTW, the old FW is pass on this item. Maybe I need to modify my setting when I use the APP to create new FW.

Hi Kedar,

I checked with GRL, we can ignore TDA 2.3.3.1 issue and the fail TD.PD.SRC3.E6 (PD3.0) is should be solved. 

Please help to check this problem.

Hi Kedar,

About TDA 2.3.3.2 , tester don't import EVB VIF so GRL report show N/A.

But GRL test the 'accept PR_SWAP_as_source' and find E3803 can't accept PR_SWAP. Is it meet the VIF of EVB?

Hi Kedar,

Anyupdate?

Hi Paul,

Sorry for my delayed response. In your project file, the second byte is 0x80, which will reject all power swaps. The bits we are interested in are bits #0 and #1 of the second byte.

Can you please try setting the second byte to 0x81 and let me know the result?

Regards,
Kedar

Hi Paul,

I missed mentioning the register address. It is 0x28 which has a 48 byte configuration data.

Regards,
Kedar

Hi Kedar,

Thank you for your reply.

I don't know how to revise the resister. I only have the application tool v4.13, I capture the screen about 0x28, please teach me which option is correct.

Hi Paul,

Please access the data using the "Raw View".

Regards,
Kedar

Hi Kedar,

Thank you for your reply.

I revised the resistor as below.

Please let me check this modify is for PD3.0 test: TD.PD.SRC3.E6. issue, right?

Hi Kedar,

Please reply my question that I ask on 3/9.

Hi Paul,

I think I earlier mentioned byte #2, but I may have made an error in mentioning that. Can you please paste your entire 48 byte data of register 0x28 here so that I can check it?

Regards,
Kedar

Hi Kedar,

I'm waiting for your reply, I need to go to GRL to double test the new FW and it need to pay GRL NTD$10000 per hour.

Please help to make sure that my modify is ok or not.

Please let me check this modify is for PD3.0 test: TD.PD.SRC3.E6. issue, right?

Hi Paul,

I had responded on 16/March. Please change the value of bits 0:1 of Byte #32 to 0x10, which will accept PR_Swaps to SInk as the Preferred Power Role.

I suggest you run this using a local tester before taking it to compliance.

Regards,
Kedar

Hi Paul,

Were you able to work with this setting? Did you try to run compliance on a local tester?

Please make sure that the compliance passes on your local tester before approaching GRL for compliance.

Regards,
Kedar

Hi Kedar,

I don't have a local tester on my company, all test report are provide by GRL for compliance test.

I already provide the new FW to GRL and they will test it today.

I will inform you once I get the test result.

Hi Kedar,

I get the test result, TD.PD.SRC3.E6 still fail.

Please see my reports as below:

 /cfs-file/__key/communityserver-discussions-components-files/138/0406-PD-retest-with-new-FW-_2600_-VIF.zip

FW change as below picture.

Hi Paul,

I quickly checked your earlier test reports (PA.zip) and it looks like TD.PD.SRC3.E6 was passing.

Is this still your latest project file: 1200.PD_VID_20200213.pjtPlease confirm.

Regards,
Kedar

Hi Kedar,

No, PD_VID_20200213.pjt is fail on TD_PD_SRC3_E6, so you suggest revise the resistor at address 0x28.

The PD_VID_20200310.pjt is the FW that revise address 0x28 and TD_PD_SRC3_E6 still ok.

TD_PD_SRC3_E6 is only pass on original FW that use old APP not version 4.13.

Below is the report (in TI BOX) and explaining.

The PD_VID_20200310.pjt is below, TD_PD_SRC3_E6 is fail.

/cfs-file/__key/communityserver-discussions-components-files/138/PD_5F00_VID_5F00_20200310.pjt

The PD_VID_20200213.pjt is below, TD_PD_SRC3_E6 is also fail.

/cfs-file/__key/communityserver-discussions-components-files/138/7652.PD_5F00_VID_5F00_20200213.pjt

Hi Paul,

The failure reason here is: "Invalid Source Capabilities Extended Data Block(SCEDB) message: Invalid Voltage Regulation field".

This means your register 0x44 (Tx Source Capabilities Extended Data Block) -> Voltage Regulation field does not match according to the tester.

You will need to match your project settings with your VIF.

The first failure was for a different reason.

Please test this and let me know. Also, it is better to have access to a local tester and confirm all pass before taking to compliance lab.

Regards,
Kedar

Hi Kedar,

Thank you for your reply.

Sorry, I don't understand what's your meaning. Could you show me the detail how to revise the setting?

BTW, the VIF is make by the TI FW tool (v4_13), why the FW setting doesn't match VIF?

Sorry, I don't have the local tester on hand. Do you have the local tester? Could you help to revise the FW base on my PD_VID_20200310.pjt and test the FW by your local tester?

If pss, please provide the FW to me.

Hi Kedar,

I checked with LAB, they tell me PD3.0 SRC.E6 fail is not related with VIF.

The test is check the field as below when DUT is capable to respond with "Source_Capabilities_Extended message".

And the problem is "Bit 0~1" shall be 00b or 01b, but DUT sets it as 11b (Reserved).

But I checked my application tool, the setting should correct. So I don't know what's going on.

Could you help to check about this issue? Why the setting if app is correct but tester read the DUT still sets it as 11b?

Hi Paul,

I will look at this and share an update next week. I don't currently have an access to 983B.

Regards,
Kedar

Hi Kedar,

Thank you for your reply.

Please share your update, two weeks passed again.

Hi Paul,

I am looking into your question. Can you confirm the version of Configuration GUI and Firmware you are currently using? The latest version in the TPS65983B Software Folder is GUI 4.14 and Firmware 6.67. There have been some changes to how the Source Extended Data Block is handled so I recommend we move to the latest version if not already..

Regards,

Scott

Hi Scott,

Thank you for your reply.

Currently, I use GUI 4.13 and Firmware 6.63. May I have the change list for GUI 4.14 and Firmware 6.67?

Could you share the latest GUI and Firmware to me?

Hi Paul, This is stored on the TI Secure Software site under my.ti and in the TPS65983 Design Folder..

Regards,

Scott

Hi Scott,

Thank you for your reply.

I tried to find the tool before, but I can't search where I can download the application tool.

Could you guide me how to download?

Thank you.

Hi Paul,

Please access the TPS65983 Design Resource Folder. You can find this under my.ti mySecure Software. Let me know if you have any problems finding this.

Regards,

Scott

Hi Scott,

I search TPS65983B in my ti as below link, but I can't find the application tool. Please guide me where it is.

https://www.ti.com/product/TPS65983B#design-development

BTW, do you see my PD compliance test report and log I sent to Kedar?

New application tool can patch  TD.PD.SRC3.E6 issue? 

Even application tool set "Source_Capabilities_Extended message" "Bit 0~1"  to 00b , but DUT sets it as 11b.

Please help to check it first, thanks.