Other Parts Discussed in Thread: DS90UR124,
Hello-
I'm using the DS90UR241 and DS90UR124 chip set to transmit a wide data path. This data is much slower than the '241's clock rate and it is also not synchronous with it. The data sheet says that the set up and hold times of the Din(0..23) inputs relative to TCLK are both a minimum of 4 ns.
In the FPGA world you are always concerned with synchronizing asynchronous inputs to avoid metastability issues. This is usually done by sending each asynchronous signal through a cascade of two or more D flip flops.
The '241 data sheet gives no indication of what the input structures look like so I can't tell if its inputs are hardened to metastability. I don't care if the signal is sampled a clock cycle late, that's not a problem. But I do care if I get a single clock cycle extra runt pulse caused by metastability. Should I be concerned with this? I could first pass the data through some 74x374 DFF's or a CPLD with a bunch of synchronizers if needed, but I'd prefer not to do that for space reasons.
Thoughts?
Thanks,
-Randy
