Other Parts Discussed in Thread: TFP401A, , TFP401
I am having difficulty determining clock to output specification (or clock to data skew specification) for the TFP401A. A similar question to the related thread. The end of the related thread says it was answered in an email so may have been clarified there but is not visible to me. Could you help me understand how to derive min and max clock to data out time?
The datasheet uses the terms setup and hold for output timing. I understand these terms on inputs but how they are to be understood for outputs pins here is unclear. The powerpoint pictures attached to the related thread ("TFP401A-Q1 AC-Timing" and "TFP401A-Q1 AC-Timing 2") relate to my questions. The illustrations there imply there is only a fixed small valid window (1.8nsec + 0.6 nsec) and the rest of a clock cycle is indeterminate. The slower the clock the more time is indeterminate. Is that the way the device works? That would seem very odd as normally a slower clock cycle results in more valid data time.
Thanks for your time!