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Original question:

TFP401A-Q1: TFP401A-Q1:maximum setup time

TFP401A-Q1: TFP401A

Ed Lamborn
Prodigy 20 points

Part Number: TFP401A-Q1
Other Parts Discussed in Thread: TFP401A, , TFP401

I am having difficulty determining clock to output specification (or clock to data skew specification) for the TFP401A. A similar question to the related thread. The end of the related thread says it was answered in an email so may have been clarified there but is not visible to me. Could you help me understand how to derive min and max clock to data out time?

The datasheet uses the terms setup and hold for output timing. I understand these terms on inputs but how they are to be understood for outputs pins here is unclear. The powerpoint pictures attached to the related thread ("TFP401A-Q1 AC-Timing" and "TFP401A-Q1 AC-Timing 2") relate to my questions. The illustrations there imply there is only a fixed small valid window (1.8nsec + 0.6 nsec) and the rest of a clock cycle is indeterminate. The slower the clock the more time is indeterminate. Is that the way the device works? That would seem very odd as normally a slower clock cycle results in more valid data time.

Thanks for your time!

  • 0
    TI__Mastermind 35130 points

    Hi Ed,

    Sorry for the delay, we hope to provide a response to this inquiry early next week.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    TI__Mastermind 35130 points

    Hi Ed,

    The slower the clock the longer the setup time for this device. I verified by looking at old characterization data that showed longer setup times at lower frequencies. The calculation in the referenced thread also roughly matches the char data. 

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 20 points

    Thank you for your response! Are you referring to the calculation shown in "TFP401A-Q1 AC-Timing 2.pptx"? Below is the calculation listed there. 

           The maximum delay is Tcycle – setup(min).

           The minimum delay is hold(min).

    Using VGA timing as an example: Tcycle = 40 nsec, setup/hold = 1.8/0.6 nsec minimums from datasheet.

    This results in clock to data out minimum delay = 0.6 nsec and maximum delay = 38.2.

    That would imply data can switch anytime within a 37.6 nsec window out of the 40 nsec cycle. It is only guaranteed to be valid for 2.4 nsec, which would seem to be constant regardless of cycle time. Can you see where I am looking at this incorrectly? You mentioned setup is longer at lower frequencies. Does that mean the datasheet min setup time is only valid for maximum clock rate (165 MHz) and min setup time can be assumed to stretch proportionately with clock cycle time increase? 

    Cheers,

    Ed

  • 0 in reply to Ed Lamborn
    TI__Mastermind 35130 points

    Hi Ed,

    The TFP401 will latch output data anytime within that 37.6 ns window, so the data should be stable within that window. 

    The datasheet min setup time was measured at 112 MHz, but yes the setup and hold time is longer at lower frequencies and longer cycle times. E.g. the char data shows a measured setup/hold time of 17.64/21.91 ns for Tcylce = 40 ns.

    Regards,

    I.K.