Interface

Interface forum

State Resolved
Locked Locked
Replies 4 replies
Subscribers 32 subscribers
Views 745 views
Users 0 members are here

Support feedback

Options

Options

Similar topics

TUSB7320: Power-up sequence of TUSB7320

Masahito Takei

Intellectual 290 points

Part Number: TUSB7320

Please tell me the timing of GRST# and PCIE_REFCLK at Power-up.

Can the PCIE_REFCLK be input after reaching the minimum recommended operating voltage and then GRST# de-asserted?

over 4 years ago

0 Masahito Takei over 4 years ago

Intellectual 290 points

Append.

On our board, PCIE_REFCLK is input immediately after VDD11 and VDDA_3P3 (and VDD3) are powered on. (See the figure below)
This is different from Figure 23. Power-Up Sequence in the data sheet. Is it acceptable?

Below: Power-up sequence of our board

0 Brian Zhou over 4 years ago in reply to Masahito Takei

TI__Guru*** 126630 points

where did you get figure 23 above? it's different from datasheet on ti.com.

PCIE_REFCLK is related to PERST#, not GRST#

0 Masahito Takei over 4 years ago in reply to Brian Zhou

Intellectual 290 points

The above figure has been modified from figure 23 of the data sheet on TI.com to our board timing (red frame).

Can PCIE_REFCLK be input before GRST# is deasserted as shown in the figure?

0 Brian Zhou over 4 years ago in reply to Masahito Takei

TI__Guru*** 126630 points

PCIE_REFCLK can be input before GRST is deasserted, make sure PSRST is low until 100ms after power supply is stable