DS90UH948-Q1: RAW_2ND_BC register function

Shinji Tsuji

Genius 14129 points

Part Number: DS90UH948-Q1

Hi team,

I have a question about UH948's RAW_2ND_BC register.

Q1. What is the purpose this register?

It is described in the datasheet as below, but could you explain what is the purpose/benefits of this feature?

For what condition do you set this bit to 1/0?

if this bit is set to a 1, the secondary back channel will operate in a
raw mode, passing D_GPIO0 from the Deserializer to the Serializer,
without any oversampling or filtering.

Q2. If you set 0x34[5] =1, does it affect the Serializer(947/949) function?

Q3. If you set 0x34[5]=1, does it affect Deserializer(948) function?

Q4. If you set 0x34[5]=1, does it affect HDCP feature?

Please advise.

regards,

over 5 years ago

0 Charley Cai over 5 years ago

TI__Genius 12866 points

Hi Tsuji,

RAW_2ND_BC is for debug purposes only and is not recommended to be set for operation.

Best Regards,

Charley Cai

0 Shinji Tsuji over 5 years ago in reply to Charley Cai

TI__Genius 14129 points

Hi Charley,

Thank you for your reply.

I found there are switching signal output from RIN1 terminal when 0x34[5] is set to 0, and it stops when it sets to 1.

In order to minimize EMI radiation, I would like to stop unintended and unused signal from the pin.

Could you advise what exactly change when 0x34[5] set to 1?

If the risk is acceptable, I would like to try set this register to minimize EMI.

regards,

0 Charley Cai over 5 years ago in reply to Shinji Tsuji

TI__Genius 12866 points

Hi Shinji,

Then I think you are just asking for a way to turn off the RIN1 back channel driver when RIN1 is not connected correct?

I can check on the proper way to do that.

Best Regards,

Charley Cai

0 Shinji Tsuji over 5 years ago in reply to Charley Cai

TI__Genius 14129 points

Hi Charley,

Yes, that is the main purpose.

regards,

0 Charley Cai over 5 years ago in reply to Shinji Tsuji

TI__Genius 12866 points

Hi Shinji,

I have check with the team and there's no proper way of turning off only port1 back channel completely.

Best Regards,

Charley Cai

0 Shinji Tsuji over 5 years ago in reply to Charley Cai

TI__Genius 14129 points

Hi Charley,

Thank you for checking the way.

When I set 0x34[5] to 1, the back channel of Port1 seems to stop.

Does this register disable Port1 back channel? Or it might start output some signal eventually?

If it can stop Port1 back channel, I would like to know the side effect of setting it to 1.

regards,

0 Charley Cai over 5 years ago in reply to Shinji Tsuji

TI__Genius 12866 points

Hi Shinji,

This doesn't power off the port 1 back channel.

It think what you saw is port 1 output a constant value of 0.

This would depend on the state of D_GPIO. Toggling D_GPIO may affect the back channel output.

Best Regards,

Charley Cai

0 Shinji Tsuji over 5 years ago in reply to Charley Cai

TI__Genius 14129 points

Hi Charly,

That is as expected. If I can control Port1 output by D_GPIO, I can manage Port1 from unexpected oscillation.

Is there any side effect setting 0x34[5] register to 1?

regards,

0 Charley Cai over 5 years ago in reply to Shinji Tsuji

TI__Genius 12866 points

Hi Shinji,

The impact should be minimal if port 1 is not used. However, please note that this is not a validated function for the devices. Please evaluate it in your system.

Best Regards

Charley Cai

0 Shinji Tsuji over 5 years ago in reply to Charley Cai

TI__Genius 14129 points

Hi Charly,

When you set that register to 0 as default and recommended, what signal output from Port1?

I confirmed it is toggling. Is this an expected behavior of this device?

regards,

0 Charley Cai over 5 years ago in reply to Shinji Tsuji

TI__Genius 12866 points

Hi Shinji,

Yeah, that's expected. That's back channel toggling.

Best Regards,

Charley Cai

0 Shinji Tsuji over 5 years ago in reply to Shinji Tsuji

TI__Genius 14129 points

Hi Charly,

The purpose of 0x34[5] utilization is EMI mitigation only and I don't want any side effect to HDCP function.

I understand I need validation of the 0x34[5] functionality, but

Could you please confirm if this bit cause any side effect to HDCP function?

I want to avoid side effect to HDCP.

regards,

0 Charley Cai over 5 years ago in reply to Shinji Tsuji

TI__Genius 12866 points

Hi Shinji,

This should have no impact to HDCP when using single FPD-Link.

Best Regards,

Charley Cai

Interface

Interface forum

DS90UH948-Q1: RAW_2ND_BC register function