DP83867IR: dp83867IR

Hi Ashok,

Can you provide me with some more background? What is your intended speed/interface/device settings?Are you strapping the device to a specific mode or performing any register writes? Are you able to link up to other link partners or none at all?

Thank you,

Nikhil

Hi Nikhil,

Here I am attaching the checklist. Please help me to solve the link establishment issue. the datasheet confusing about the strap options.

Thanks & Regards,
--Ashok0451.DP83867_Schematic_Design_Review_Checklist.xlsx

Hi Ashok,

What is the part number for the RJ-45 connector? Does it include integrated magnetics? I see 47 ohm resistors on each pin in the RJ-45 section, have you tried shorting these?

Thank you,

Nikhil

Hi Nikhil,

RJ45 part no: 2250015-3 having internal magnetics and used in another project interfaced with marvell chipset.

currently the r47ohm is not using. Provided provision to have ac termination. Please provide proper starpping and phy_add setting.

Thanks,

--Ashok

Hi Ashok,

This RJ-45 part shorts the center taps of the magnetics which is not recommended for the DP83867. There should also be no pull-up on the center taps. We recommend changing the magnetics such that the center taps are not shorted together and removing the pull-up. As an experiment, you may leave the current RJ-45 for now and try disconnecting this pull-up while also removing the 47 ohm resistors. 

Thank you,

Nikhil

Hi nikhil,

There should also be no pull-up on the center taps. We recommend changing the magnetics such that the center taps are not shorted together and removing the pull-up.

-- Theses pull ups are internal to the RJ45 connector

As an experiment, you may leave the current RJ-45 for now and try disconnecting this pull-up while also removing the 47 ohm resistors.

-- We already removed the 47ohm resistor on the board.

We even trying to read the phy_id external with MSP430G2C but i am not getting it.

Thanks & Regards,

--Ashok

Hi Ashok,

Is it possible to use a different RJ-45 without the internal pull-ups? Limiting the deviations from the datasheet will help narrow down the problem. 

Some background questions: What is your intended speed/interface/device settings?Are you strapping the device to a specific mode or performing any register writes? Are you able to link up to other link partners or none at all?

If you are able to read the registers, can you provide me the following register values:

register 0x0000

register 0x0001

register 0x0011

 If you have access to the MDIO/MDC pins you may try using our USB-2-MDIO tool. 

Thank you,

Nikhil

Hello Nikhil,

Is it possible to use a different RJ-45 without the internal pull-ups? Limiting the deviations from the datasheet will help narrow down the problem.  - Will try after checking with USB-2-MDIO tool

Some background questions: What is your intended speed/interface/device settings?Are you strapping the device to a specific mode or performing any register writes? Are you able to link up to other link partners or none at all?

If you are able to read the registers, can you provide me the following register values:

register 0x0000 - 1140

register 0x0001 - 7949

register 0x0011 - 0302

 If you have access to the MDIO/MDC pins you may try using our USB-2-MDIO tool. - Samething we started doing.

Thanks,

--Nikhil

Hi Ashok,

Can you provide me with a schematic?

Thank you,

Nikhil

Hello Nikhil,

1. I am able establish the link but it is taking some time to establish the link. In the RJ45 the center tapped pins connected to capacitors and the capacitors one end is connected to VCC. I removed the VCC pin in the connector then the link is established.

2. I loaded the xilinx provided lwip application code. During it's run time link up and link down problem is coming.

3. it's connecting to only 100Mbps and ping is working, for other speed as 10 and 1000Mbps it's not able to ping.

Could you please suggest or provide Ethernet application code which ti developed for artix 7 fpga.

Thanks & Regards,

--Ashok

Hi Ashok,

To confirm the procedure:

1. PHY power on, link is up

2. Run Xilinx code, then link issues occur

Is the Xilinx code changing any register settings?

If you are able to run Linux, we have a driver for the DP83867 available here: https://www.ti.com/tool/ETHERNET-SW. Please let me know if you're able to establish link at all speeds using this driver.

Thank you,

Nikhil

Hi nikhil,

1. Now phy pinging is working for 10 and 100Mbps speed. we have changed small piece of code in the lwip mail, start_application for creating server. Then continuously i am able to ping for both 10/100 Mbps.

2. Link is established for 1000 Mbps but when i load the code link is not stable. Link up and Link down is coming.

Could you please send any one else faced the same issue.

Thanks,

--Ashok

Hi nikhil,

I have been waiting for your reply almost it's 4 days over. could you please reply on that.

Thanks,

--Ashok

Hi Ashok,

Thank you for your patience. To try to narrow down the problem, I have the following questions:

1. What type of cable are you using? How long of a cable?

2. What is the link partner? Does this happen across all link partners?

3. Previously, at 10 Mbps, the PHY was not linking correct? What changes did you make to the PHY registers to get 10 Mbps speed working?

Thank you,

Nikhil