Other Parts Discussed in Thread: USB-2-MDIO
I am working on a Prototype Dev board. We used a BeaglBone Black, then the Octavo RED, as Proof of Concepts to develop software for a prototype system. We are using Octavo's OSD3358-SM which is a nice SIP. I have everything working on our prototype...except Ethernet.
A Staff Electrical Engineer designed the board.
Dev Laptop: Linux Mint.
/dts-v1/;
#include "osd335x-sm.dtsi"
#include <dt-bindings/display/tda998x.h>
#include <dt-bindings/net/dp83867.h>
…..
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_txd3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_txd2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_txclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rxclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
/* Slave 2 */
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_txd3 */
AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_txd2 */
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_txd1 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_txd0 */
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_txclk */
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rxclk */
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rxd3 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rxd2 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rxd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rxd0 */
>;
};
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 */
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
};
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
slaves = <2>;
status = "okay";
dual_emac;
};
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <1>;
};
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <2>;
};
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti-dp83867-rxctl-strap-quirk;
};
dp83867_1: ethernet_phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti-dp83867-rxctl-strap-quirk;
};
};
My syslog shows the following:
[ 1.119507] libphy: 4a101000.mdio: probed
[ 1.142730] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver unknown
[ 1.142747] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver unknown
[ 1.144089] cpsw 4a100000.ethernet: Detected MACID = 60:64:05:4f:81:d4
[ 1.144237] cpsw 4a100000.ethernet: initialized cpsw ale version 1.4
[ 1.144247] cpsw 4a100000.ethernet: ALE Table size 1024
[ 1.144303] cpsw 4a100000.ethernet: cpts: overflow check period 1250 (jiffies)
[ 1.145418] cpsw 4a100000.ethernet: cpsw: Detected MACID = 60:64:05:4f:81:d6
[ 15.662192] Generic PHY 4a101000.mdio:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[ 15.709970] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 15.784052] net eth1: initializing cpsw version 1.12 (0)
[ 15.816577] Generic PHY 4a101000.mdio:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=4a101000.mdio:01, irq=POLL)
[ 15.850318] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 16.673405] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[ 16.673481] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 17.005200] 8021q: 802.1Q VLAN Support v1.8
[ 17.005287] 8021q: adding VLAN 0 to HW filter on device eth0
[ 17.005399] 8021q: adding VLAN 0 to HW filter on device eth1
[ 37.313404] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[ 39.361286] cpsw 4a100000.ethernet eth1: Link is Down
[ 39.426953] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 59.841154] cpsw 4a100000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
[ 59.841230] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[ 61.888955] cpsw 4a100000.ethernet eth1: Link is Down
[ 61.931069] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
I based my Overlay from Octavo's Device Tree files, or osd3358-bsm-refdesign.dts. So I'm using their "osd335x-sm.dtsi"
Everything I have configured works (I2C, SPI, Audio Codec, etc) except Ethernet. I even changed the freq to 2.5MHz in the dtsi. When my kernel loads, it defaults to Generic PHY as shown above for eth0 and eth1....and to 1Gbps at full but I do not get a 1Gbps light. I also cannot ping or SSH into my proto board. I can ping localhost but not another laptop when I change the /opt/network/interfaces for eth0 to be static with an ip address and subnet. If I change the "reg= <0>" or "reg = <1>" to anything else, it doesn't load the PHY at all (-err 19). The dual DP83867s are strapped for mode 1, reg 0 and reg 1.
I used the dra71-evm.dts to help me understand how to set up for a DP83867.
I even tried manually loading the driver (sudo modprobe dp83867) and it will show up in "lsmod" list of modules but not used by anything. Even after setting my ip link down and up, it still only loads the Generic PHY driver. I also tried every clock skew setting in the device tree node, from 250 ps to 4 ns.... nothing changes it.
To me, it looks like MDIO is not associating the Driver to my settings. The board designer is measuring the MDIO trace lengths. We are using an oscilloscope to look at the data now.
Does my device tree settings look correct to load the DP83867 module?
Could the MDIO lines be too long or out of tolerance on the board and be creating a skew I can't account for in configuration?
Has anyone else seen this issue?