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DP83867IR: DP83867 modules not showing up when configured.

Part Number: DP83867IR
Other Parts Discussed in Thread: USB-2-MDIO
All,
I am working on a Prototype Dev board. We used a BeaglBone Black, then the Octavo RED, as Proof of Concepts to develop software for a prototype system. We are using Octavo's OSD3358-SM which is a nice SIP. I have everything working on our prototype...except Ethernet.

A Staff Electrical Engineer designed the board.
OS= BBB-debian-9.9-lxqt-armhf-2019-08-03.
Dev Laptop: Linux Mint.
I developed my own overlay by editing Octavo's, see snippet below dealing with ethernet:
 /dts-v1/;
 #include "osd335x-sm.dtsi"
 #include <dt-bindings/display/tda998x.h>
 #include <dt-bindings/net/dp83867.h>
…..
cpsw_default: cpsw_default {
  pinctrl-single,pins = <
    /* Slave 1 */
    AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
    AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
    AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_txd3 */
    AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_txd2 */
    AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
    AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
    AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_txclk */
    AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rxclk */
    AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rxd3 */
    AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rxd2 */
    AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
    AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
 
    /* Slave 2 */
    AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)        /* gpmc_a0.rgmii2_tctl */
    AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)         /* gpmc_a1.rgmii2_rctl */
    AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)        /* gpmc_a2.rgmii2_txd3 */
    AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)        /* gpmc_a3.rgmii2_txd2 */
    AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)        /* gpmc_a4.rgmii2_txd1 */
    AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)        /* gpmc_a5.rgmii2_txd0 */
    AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)        /* gpmc_a6.rgmii2_txclk */
    AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)         /* gpmc_a7.rgmii2_rxclk */
    AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)         /* gpmc_a8.rgmii2_rxd3 */
    AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)         /* gpmc_a9.rgmii2_rxd2 */
    AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)         /* gpmc_a10.rgmii2_rxd1 */
    AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)         /* gpmc_a11.rgmii2_rxd0 */
 >;
};
cpsw_sleep: cpsw_sleep {
  pinctrl-single,pins = <
    /* Slave 1 reset value */
    AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
    /* Slave 2 */
    AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)        
    AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)       
    AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)        
    AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)        
    AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)        
  >;
};
davinci_mdio_default: davinci_mdio_default {
  pinctrl-single,pins = <
    /* MDIO */
    AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
    AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_clk.mdio_clk */
  >;
};
davinci_mdio_sleep: davinci_mdio_sleep {
  pinctrl-single,pins = <
    /* MDIO reset value */
    AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
    AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  >;
};
&mac {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
        slaves = <2>;
        status = "okay";
        dual_emac;
};
&cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
        phy-mode = "rgmii-rxid";
 dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
 phy_id = <&davinci_mdio>, <1>;
        phy-mode = "rgmii-rxid";
        dual_emac_res_vlan = <2>;
};
&davinci_mdio {
        pinctrl-names = "default", "sleep";       
        pinctrl-0 = <&davinci_mdio_default>;       
        pinctrl-1 = <&davinci_mdio_sleep>;
        status = "okay";
        dp83867_0: ethernet_phy@0 {
            reg = <0>;
            ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
            ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
            ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
            ti,min-output-impedance;
            ti-dp83867-rxctl-strap-quirk;
 };
       
        dp83867_1: ethernet_phy@1 {
            reg = <1>;
            ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
            ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
            ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
            ti,min-output-impedance;
            ti-dp83867-rxctl-strap-quirk;
        };
   
};

My syslog shows the following:
[    1.119483] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 2500000
[    1.119507] libphy: 4a101000.mdio: probed
[    1.142730] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver unknown
[    1.142747] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver unknown
[    1.144089] cpsw 4a100000.ethernet: Detected MACID = 60:64:05:4f:81:d4
[    1.144237] cpsw 4a100000.ethernet: initialized cpsw ale version 1.4
[    1.144247] cpsw 4a100000.ethernet: ALE Table size 1024
[    1.144303] cpsw 4a100000.ethernet: cpts: overflow check period 1250 (jiffies)
[    1.145418] cpsw 4a100000.ethernet: cpsw: Detected MACID = 60:64:05:4f:81:d6
[   15.628693] net eth0: initializing cpsw version 1.12 (0)
[   15.662192] Generic PHY 4a101000.mdio:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[   15.709970] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   15.784052] net eth1: initializing cpsw version 1.12 (0)
[   15.816577] Generic PHY 4a101000.mdio:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=4a101000.mdio:01, irq=POLL)
[   15.850318] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[   16.673405] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[   16.673481] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[   17.005200] 8021q: 802.1Q VLAN Support v1.8
[   17.005287] 8021q: adding VLAN 0 to HW filter on device eth0
[   17.005399] 8021q: adding VLAN 0 to HW filter on device eth1
[   37.313323] cpsw 4a100000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
[   37.313404] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[   39.361286] cpsw 4a100000.ethernet eth1: Link is Down
[   39.426953] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[   59.841154] cpsw 4a100000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
[   59.841230] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[   61.888955] cpsw 4a100000.ethernet eth1: Link is Down
[   61.931069] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready

I based my Overlay from Octavo's Device Tree files, or osd3358-bsm-refdesign.dts. So I'm using their "osd335x-sm.dtsi"

Everything I have configured works (I2C, SPI, Audio Codec, etc) except Ethernet. I even changed the freq to 2.5MHz in the dtsi. When my kernel loads, it defaults to Generic PHY as shown above for eth0 and eth1....and to 1Gbps at full but I do not get a 1Gbps light. I also cannot ping or SSH into my proto board. I can ping localhost but not another laptop when I change the /opt/network/interfaces for eth0 to be static with an ip address and subnet. If I change the "reg= <0>" or "reg = <1>" to anything else, it doesn't load the PHY at all (-err 19). The dual DP83867s are strapped for mode 1, reg 0 and reg 1.

I used the dra71-evm.dts to help me understand how to set up for a DP83867.
I even tried manually loading the driver (sudo modprobe dp83867) and it will show up in "lsmod" list of modules but not used by anything. Even after setting my ip link down and up, it still only loads the Generic PHY driver. I also tried every clock skew setting in the device tree node, from 250 ps to 4 ns.... nothing changes it.

To me, it looks like MDIO is not associating the Driver to my settings. The board designer is measuring the MDIO trace lengths. We are using an oscilloscope to look at the data now.
Does my approach seem logical, do I have to make changes to u-boot also?

Does my device tree settings look correct to load the DP83867 module?

Could the MDIO lines be too long or out of tolerance on the board and be creating a skew I can't account for in configuration?

Has anyone else seen this issue?
Any help would be appreciated. I can't post schematics.
  • Hi Ray,

    To try and narrow down the issue I have the following questions:

    1. What is the bootstrap on RX_CTRL?

    2. How have you strapped the PHY address?

    3. How have you strapped the LED's? Are you only checking the LED's to check for link or are you checking the PHY_STS register?

    4. Are still able to read and write registers?

    5. What is the pull-up on the MDIO line?

    Thank you,

    Nikhil

  • I will try to get all those specifics on Monday. We are using two PHY ICs. One is strapped for reg 0, the other 1. And the RX/TX lines are not strapped for mode 1. I have not attempted to read any mdio registers. Can it be done from linux terminal, I've never done that?

    I was able to force the kernel to boot using the DP83867 Driver by adding “CONFIG_DP83867_PHY=y” to /u-boot/configs/am335x_evm_defconfig.txt file and compiling on the laptop using the “gcc-linaro-6.5.0-2018.12-x86_64_arm-linux-gnueabihf” cross compiler. It shows as active in "lsmod" modules readout and in syslog it shows both phys assigned to dp83867 driver.

    I still cannot ping or SSH the Dev board from my laptop by setting a static IP address (ie 192.168.10.1) and updating /etc/network/interfaces on the Dev board to make eth0 static with a matching IP address (ie 192.168.10.2).  I now noticed when I add my overlay as active, it will drop out the USB virtual connection now. I was thinking slaves = <2>; would fix it in the device tree for MAC. Nope.

    But...There has to be some kind of negotiation going on as when it was loading the Generic PHY it would default to 1Gps Full, but now only goes to 100Mbps Full.

    Using my laptop with "tcpdump" I never get an ARP or packets  with my dev board IP Address. I would think if I was  not connecting at all though, I would only get a 10Mbps connection.

  • Hi Ray,

    You may read the registers through the MDIO/MDC pins with our USB-2-MDIO tool. This may be useful for debug, rather than adding read statements to your linux code. This forum focuses on the Physical Layer, so as we wait for the specifics on your hardware setup, you may want to post this question on processor forum in parallel.  

    Thank you,

    Nikhil

  • Nikhil,

    1. What is the bootstrap on RX_CTRL?  Strapped with a 5.76k Ohm (to 3.3v) and 2.49k Ohm (to DGND). This should put it in Mode 3 (Auto Neg On).

    2. How have you strapped the PHY address? Our PHY1 = 0 (No Strap). Our PHY2 = 1, RXD0 strapped with 2.49k Ohm (to DGND) and 10k Ohm (to 3.3v).

    3. How have you strapped the LED's? Are you only checking the LED's to check for link or are you checking the PHY_STS register?

    LED0 = No strap - just 560 Ohm resistor, LED1 = Strapped with 2.49k Ohm (to DGND) and 560 Ohm (to 3.3v), LED2 = No strap - just 560 Ohm resistor.

    Just watching link status.

    4. Are still able to read and write registers? I'm still looking into this using the USB-2-MDIO tool.

    5. What is the pull-up on the MDIO line? Has a 2.2k Ohm resistor.

     

    Additionally, I think I found that the latest Bone Debian (9.9) has an issue with bringing up the driver for the DP83867. I reverted back to an earlier version (9.1) and it seemed to auto detect the IC and bring up the driver. I'm going to load a fresh install of both with no u-boot edits and see if it associates the DP83867 driver automatically. 

  • Hi Ray,

    Thanks for your update. Just to confirm again, are you are using a custom driver or our linux driver linked here: https://www.ti.com/tool/ETHERNET-SW.

    Please give me an update in regards to using the earlier version of Bone Debian and using the USB-2-MDIO tool. 

    Thank you,

    Nikhil 

  • Nikhil,

    Thanks for the help in this issue. We found the issue and now ethernet is working, but only at 10/100. I'm going to work with adjusting the Tx/Rx delay skews in the device tree to see if that can get us a 1G link.

    As for your last question, yes we were using the correct driver. The correct driver is now substantiated by the device tree (verified in our syslog readout). We used the u-boot menu to read MDIO registers and they were all correct via mode 3 we configured.

    So what fixed it? It ended up being a Bone Debian OS issue...or misunderstanding of configuring the network interfaces correctly. Embedded Debian development comes with the standard network manager to use ifconfig or simply edit the etc/network/interfaces config file.

    They also added connmanctl (link here to more info), which is a network manager on top of the typical network manager. So simply going into the Linux terminal and typing in $ sudo ifconfig eth0 192.168.10.1 netmask 255.255.255.0 up is not enough. You have to also tell connmanctl to allow the service (ethernet device) to be approved to use the network.

    What you have to do first is get the service name that connmanctl assigns to eth0 and/or eth1. Which can only be done if ifconfig is used to configure the eth0 first and you are actually connected to another device (like a switch). You get the ethernet service name in the terminal via $ connmanctl services.  But wait, that's not all. You have to now configure that network service the same as you configured eth0 with ifconfig via $ sudo connmanctl <ethernet service> --ipv4 manual 192.168.10.1 netmask 255.255.255.0 gateway <gateway addr>

    And it gives the service a long name like ethernet_6064054f81d8_cable

    The best thing to do is edit the etc/network/interfaces config file. It has a section to set up the ethernet similar to ifconfig and another to configure connmanctl services during bootup. I done this and it works. Crazy that embedded Debian is using, what is essentially, two network managers. I'm going to make a build of embedded debian and see if removing connmanctl (sudo apt remove) letting ifconfig work to set everything up. 

  • Hi Ray,

    Thanks for the information! As a quick check, is the driver changing register 9 or writing to any other registers? Also as a sanity check, can you confirm that the link partner supports 1G communication?

    Thank you,

    Nikhil