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PCA9518: About Vilc - Vol @PCA9518

teritama
Expert 2390 points

Part Number: PCA9518

Hi team.

We use this device for SMBus.

However, during the battery discharge, SCL(SMBC) clock signal don't  become High level like follow figure. 

We infer this problem is caused by Vilc - Vol  falls below 70mV due to the noise generated by this application.

Immediately before the rise of the clock, noise  is superimposed, causing noise above 70 mV to be mistakenly recognized as Vol on the slave side.

We want some information about pulse width or peak voltage to not misrecognize.

Do you have some information or how to deal with similar devices and similar cases?

best regards

  • 0
    TI__Guru 53535 points

    Hi Teritama-san,

    I see that there appears to be a glitch on SCL during the battery discharge and you believe the problem is related to the offset voltage created by PCA9518. 

    If possible, could you share what the input SCL signal looks like (Master driven I2C lines)? I am curious if PCA9518 is having trouble re-driving the signal or the input signal is distorted which causes the faulty output. I suspect this because the timing between the rising edge of the bit after the faulty clock bit is not consistently spaced from previous bits. 

    Because PCA9518 does not recognize I2C logic (only propagates based on voltage levels), the pulse width recognition is based on propagation delay and transition time.  

    Sharing a schematic would likely make describing the layout easier. If you would like to share this offline, please find my email in my E2E profile. 

    Regards,
    Eric

  • 0 in reply to Eric Schott1
    Expert 2390 points

    Hi Eric-san,

    I sent email for you same title with this question.

    Please check input SCL signal and schematic.

    Best regards,