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DS25CP102: EQ gain when EQ off setting

Takashi Onawa
Genius 13200 points
Part Number: DS25CP102

Hi Team,

My customer sometimes gets CRC error in their system used  DS25CP102. I couldn't see anything strange as far as I check their board. Since an error often occurs when a signal of a specific pattern is received, it might be caused by over-equalization.

Then I have some questions.

1. Could you check if DS25CP102 has weak EQ gain even in state of EQ OFF?

2. Do you have a good idea to increase the LOSS of the signal DS25CP102 receive? I want to try that to find out the rood cause of this issue.

Regards,

Takashi Onawa

  • 0
    TI__Guru* 93670 points

    Hi Onawa-San,

    1- Please note figure 14 and 15 of the data sheet. With EQ off, at maximum we can have 20ps of jitter across supply and data rate. At highest data rate - 4Gbps - this is about 80mUI of jitter and this is very negligible. 

    2- Please note incoming signal eye diagram could be closed and then device applies EQ gain transfer function. So as long as signal loss characteristics is like what is noted in Test Channel Loss Characteristics table we should be able to equalize the incoming signal.

    You noted CRC error occurs when a signal of specific pattern is received. Can you specify pattern details when we have error versus when there is not error ?

    Regards,, Nasser