Hi TI Engineers,
In Hardware testing,we fould two questions in power up timing.T5.3 and T5.5 is over limits.
1) T5.3
Our board is 827us,TI's EVM board is 1300us.All are over 350us.
We want to know the max time for T5.3.
2)T5.5
Our board is 206ms.We control MDC after system keeping steady.So time is over 60ms.
Has it bring some risks if T5.5 over limits?