TUSB1310 TCLK Signal

Wes,

Thanks for the clarification. Appart from the clock frequency, is there any phase relationship requirement between TCLK and PCLK or are the two buses (Rx and Tx) completely independent?

James

One is an input and the other is an output, my understanding is that they are completely independent.  I see no way there could be a phase relationship.

-wes

Great, thanks for the help.

James

Does this imply that the PCLK is the clock source for the RX_DATA and RX_DATAK lines?

In our prospective design, would this mean that we would need two clock signals going into our FPGA and/or ASIC?

N

Nevermind, I just realized that PCLK is an output while TCLK is an input.  Based on a few other threads related to this part, I've learned that we can directly connect the PCLK to the TCLK line.

With that said, I'm now a little confused about the CLKOUT pin.  My understanding is that it should be synchronized with the PCLK except in U3 (power state) mode.  This way, it is able to tell the link controller the system timing as seen by the USB chip.  Is this correct?

Hello,

Not exactly,

The CLKOUT output is enabled only when the TUSB1310A is in U3, this way the PHY will be able to tell the Link layer when a wake-up event has occur.

Regards.

Interesting.  To ensure that I understand what you said: the CLKOUT isn't an actual clock signal and instead is a digital line that is only active when the TUSB1310A chip is in U3 mode?  Therefore, when the TI chip leaves the U3 mode, it deasserts that CLKOUT pin and that is how the link layer knows when the wake-up event occurred?