I have the following two questions regarding implementation of the DS160PR410 in a PCIe x4 gen 2 setting.
1. The Datasheet indicates that "At power up, after a manually triggered event through PWDN1 and PWDN2 pins (in pin mode), ... , the redriver determines whether or not a valid PCI express termination is present at the far end of the link."
If no event occurs on the PWDN pins (eg: if these pins are shorted to GND), will the redriver still attempt to detect valid termination of a connected endpoint?
2. Is the Buffer expected to be powered prior to the PCI subsystem powering on and establishing links? For example, should the buffer be allowed to power up and configure itself in pin mode, prior to powering of the Root complex and endpoint?
Thank you for any insight that you can provide.