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DS160PR410: PWDN pin strapping, Power-up timing

Part Number: DS160PR410

I have the following two questions regarding implementation of the DS160PR410 in a PCIe x4 gen 2 setting.

1. The Datasheet indicates that "At power up, after a manually triggered event through PWDN1 and PWDN2 pins (in pin mode), ... , the redriver determines whether or not a valid PCI express termination is present at the far end of the link."

If no event occurs on the PWDN pins (eg: if these pins are shorted to GND), will the redriver still attempt to detect valid termination of a connected endpoint? 

2. Is the Buffer expected to be powered prior to the PCI subsystem powering on and establishing links? For example, should the buffer be allowed to power up and configure itself in pin mode, prior to powering of the Root complex and endpoint?

Thank you for any insight that you can provide.

  • Hi Ryan,

    The PWDN pins are level sensitive.  If they are shorted to GND the DS160PR410 will be stuck in "normal operation".  Within this mode of operation the RX_DET pin will control the receiver detect function.  See Table 3 in the datasheet for details.

    The buffer (DS160PR410) is expected to receive power at the same time as the Endpoint or Root Complex.  There is no need to power it on early and initialize it before the rest of the system is powered up.

    Regards,

    Lee

  • Thank you for the clarifications, Lee!

    For further clarification on the PWDN pins- What is the "Manually triggered event" on the PWDN pins that section 7.3.3 of the datasheet refers to? Does the device expect to see a level change on these pins at power up when an endpoint is connected, or only in the case of a hot plug?

  • Sorry for the delay.  The manually triggered event is just a Low - High - Low sequence on the PWDN pins.

    At power up the device will automatically trigger as long as the PWDN pins are held Low.

    Regards,

    Lee