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DS90UB941AS-Q1: Minimum pixel clock consideration when symmetric splitting

RYO
Intellectual 2000 points
Part Number: DS90UB941AS-Q1

Hi all,

I would like to know how to consider the minimum pixel clock when symmetric splitting mode. When outputting the 2xWVGA (800x480, 60fps, 23MHz pixel clock), the input can satisfy the device minimum pixel clock of 25MHz. However, the output of the pixel clock of 23MHz and the both output data rates of 368.640Mbps when 16bit and 414.720Mbps when 18bit cannot satisfy the 875Mbps minimum which is written in datasheet 8.3.2. How can we manage this?

Regards,
RYO

  • 0
    TI__Guru** 103215 points

    Hello RYO,

    The 941AS supports minimum 25MHz PCLK per channel as per the datasheet:

    23MHz PCLK is not including any blanking for the image so once you add in blanking it is likely that the PCLK for 800x480@60 will go over 25MHz in which can it can be supported. 

    Best Regards,

    Casey