Hi,
We've built a custom board with a DS90UB960. I've been able to configure CSI Port 0 to generate a test pattern successfully. Now I would like to do the same on CSI Port 1. I've attempted to program the part in the same way by selecting the TX Port with the CSI_PORT_SEL register. When I enable the CSI1 port with the CSI_CTL register, I see the clock and data lines enter the low power state (ie, the both are driven to about 1.2V or so). When I enable the pattern generator, there is signal present. It is just crickets.
The documentation in the datasheet regarding the test pattern is rather vague whether both ports are supported. There are certain places in the datasheet where it only refers to CSI Port 0 for the pattern generator and other places where it refers to both ports. Can anyone tell me whether it is possible to generate a test pattern on CSI Port 1?
Is there a bit that needs to be configured to send the pattern generator messages to CSI port 1 instead of CSI port 0?
