• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 477 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS250DF810EVM: DS250DF810EVM

Tom Roe68
Prodigy 130 points
Part Number: DS250DF810EVM
Other Parts Discussed in Thread: DS250DF810

Has anyone got the ds250DF810EVM or similar 28G part to CDR lock on 10.3125 G KR? The 10G I use is from a FPGA and can loop back to itself through the same wires I use for the EVM board. The FPGA loopback does better than 1E-15 BER. When I bring those wires to the EVM it gets a signal detect but hardly ever a CDR lock. When I do an eye diagram at 400mv range it swamps screen with red with a very small opening in different places. It looks almost like I am not using 10.3125G but I verified it on the FPGA loopack with a Xilinx iBert.  I tried reducing the output amplitude of the FPGA to 320mV thinking I was over equalizing but that did nothing. At 170mV output it lost signal detect so I would think that I did not over equalize it at 320mV. Any suggestions would be great. Thanks

  • 0
    TI__Mastermind 19235 points

    Hi,

    The DS250DF810 should be able to lock to 10.3125Gbps data once its CDR is programmed to the correct rate setting. Channel register 0x2F[7:4] should be set to 0x0 for 10.3125Gbps operation. See questions below to assist me in troubleshooting?

    • What is the approximate DS250DF810 retimer input channel insertion loss for 10.3125Gbps?
    • What values are you observing for the following channel registers when the retimer does achieve CDR lock?
      • 0x02, 0x27, 0x28, 0x31, 0x8F

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 130 points

    Hi Rodrigo,

    Insertion loss is probably low, maybe 2-3 dB at 10.3125. It is from a Xilinx eval board through the Huber Suhner cable to your board so I don't have sim numbers for that. I did try putting in a lossier cable but that did not work either. I do get a link at 10G and a CDR lock, it looks like the GUI was not setting the bit rate properly even though I hit the radio button for 10.3125. Now that I double check the 10.3125 is set it locks on some of the time.

    I am getting a really bad BER of 1e-8 on the Xilinx iBert and the eye is really bad on your gui.

    x02  xD8

    x27  x10

    x28   xB0

    x31  x20

    x8F  xD8

    I was changing the DFE and CTLE to get a lock but as I said the BER and eye is terrible.

    Any other suggestions would be helpful.

    Thanks

    Tom

  • 0 in reply to Tom Roe68
    TI__Mastermind 19235 points

    Hi,

    Thanks for the system level info. I believe the issue here is signal over-equalization at the retimer input given the low input channel loss. I would recommend to evaluate the following TI retimer settings:

    • Force a CTLE boost setting of 0x00.
    • Enable CTLE limiting output mode
    • Lower the retimer EQ bias current to reduce the applied CTLE boost at setting of 0x00

    See the channel register routine below

     

     

    STEP

    SHARED/ CHANNEL REGISTER SET

     

    OPERATION

     

    REGISTER ADDRESS [HEX]

     

    REGISTER VALUE [HEX]

     

    WRITE MASK [HEX]

     

    COMMENT

    1

    Channel

    Write

    2D

    08

    08

    Enable CTLE boost override

    2

    Channel

    Write

    03

    00

    FF

    Set CTLE boost to 0x00.

    3

    Channel

    Write

    13

    04

    04

    Set EQ_LIMIT_EN=1 (limiting output mode)

    4

    Channel

    Write

    1A

    00

    08

    Reduce CTLE bias current

    Cordially,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 130 points

    This helped it lock on. I guess the power input is too high like you said. Thanks for your help.

    One more question before I mark this done.

    I need to use this part in fanout mode. It seems like when I lose CDR lock, the second channel I am fanning out to goes off. when both channels are locked the broadcast works. Do you know if the part needs to be clock locked before it fans out the input signal? I can't find a register setting that would affect this.

    Thanks

    Tom

  • 0 in reply to Tom Roe68
    TI__Mastermind 19235 points

    Hi,

    The DS250DF810 cross-point block is located before the CDR, so its configuration is not affected by it. However by default the retimer channel output is muted when CDR is not locked.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer