This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83TC811S-Q1: two question about Slave and Master in SGMII mode

Part Number: DP83TC811S-Q1

Hi Team,

There are two questions may need your help..

  • When using SGMII mode, how to configure master or slave? Customer has tried P46 in datasheet to configure LED0 and LED1 but failed.

Maybe I could just ask them to configure by setup PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2?

  • If in the same PHY,  hardware set as slave but software set as salve, which mode actually the PHY is? Master or Salve? 

Will it cause software return error? Customer now receive such a error:"Kernel log shows that the clock between phy and MAC is not on lock; sgmii CDR not lock"

  • Hi Amelie,

    Please help with the following information for further debug :

    1. What is the value being read of register 0x0834 when straps are not latched properly?

    2. Can you also ask the customer to remove LED connected to the LED0 pin (if any) and then check is strapping is happening correctly
    ?

    3. What is the value being read of register <0x0467> and register<0x0468>? 

    Writing through software after power up will over-ride the hardware configuration latched during power up.

    Error being highlighted here looks to be related to Sgmii and if so it should be independent of master or slave configuration as sgmii is independent of MDI side configuration (master/slave). What is the status of link register 0x0001 and 0x0133>

    --

    Regards,

    Vikram