Hi Team,
I have some questions for MIPI CSI output.
#1.
Does CSI output become Hiz?
Are there any conditions such as a temporary HiZ at power-on?
#2.
If #1. is Yes, please tell me the timing chart and the conditions for HiZ.
In our system, it has been found that the SoC on the receiving side cannot operate normally when the CSI becomes HiZ.
We need to know if this situation can happen in 954.
Best regards,
Tomoaki Yoshida
