DP83867IR: GPIO behavior when WoL and IEEE_1588_SFD_TX/Rx are assigned to GPIO pin

Takahiro Saito

Part Number: DP83867IR

Hi team

Datasheet 8.3.1 describes that a signal on GPIO is generated when qualifying signal is received in WoL configuration.
Could you explain more detail of the behavior of GPIO when magic packet is detected?

1. What is the initial state when DP83867 is waiting magic packet, low or high ?
2. When the magic packet is detected, how much is the duration of GPIO output?
3. Is this GPIO pin CMOS output or open-drain ?

Also, could you explain more detail of the behavior of GPIO when IEEE_1588_SFD_Tx and Rx is assigned to GPIO as well?

1. What is the initial state when DP83867 is waiting start-of-frame, low or high ?
2. When the start-of-frame is detected, how much is the duration of GPIO output?
3. Is this GPIO pin CMOS output or open-drain ?

Regards,
Saito

over 5 years ago

0 Nikhil Menon over 5 years ago

TI__Genius 11725 points

Hi Saito,

To answer your questions regarding WoL:

1. The initial state of the GPIO will be low. The interrupt signal received will be high.

2. The pulse length can be configured through RXFCFG Register 0x0134

3. GPIO pins are CMOS

When configuring GPIO pins for SFD pulses, the behavior is similar.

Thank you,

Nikhil

0 Takahiro Saito over 5 years ago in reply to Nikhil Menon

TI__Expert 5455 points

Hi Nikhil,

Thanks!

Regards,

Saito

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DP83867IR: GPIO behavior when WoL and IEEE_1588_SFD_TX/Rx are assigned to GPIO pin