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TUSB9261-Q1: The minimum reset pulse

Tomoaki Yoshida91
Genius 5255 points

Part Number: TUSB9261-Q1

Hi Team,

What is the low pulse width that the GRZ recognizes RESET surely?

That is, the minimum pulse width guaranteed by the device.

What happens if a shorter pulse is input?

For example, I want to know if it will not cause malfunction or destruction, if a short pulse is ignored and nothing happens, and what kinds of cases are possible.

I expect that a pulse slightly smaller than the guaranteed value will reset, but more smaller pulses will be ignored and nothing will happen.

The following is described in the power up and reset sequence of the data sheet.

A minimum reset duration of 1 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the de-assertion of GRSTz.”

This means that the time from when the power supply stabilizes to when reset is released is at least 1 ms.

Is this correct?

Are there any restrictions on reset during power down?

Best regards,

Tomoaki Yoshida

  • 0
    TI__Guru**** 158955 points

    you are right, 1ms is the min pulse for device to get reset, but suggest for 2ms when you design the system.

  • 0 in reply to Brian Zhou
    Genius 5255 points

    Hi Brian-san,

    Thank you for your reply.

    I understand that the 1ms pulse width is a guaranteed value for the device.

    What happens if the pulse width goes below 1ms?

    How do you think this is?

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    Genius 5255 points

    Hi Brian-san,

    I have a question about power-up and power-down rules.

    Please check  the following document:

    /cfs-file/__key/communityserver-discussions-components-files/138/power-up-sequence.pdf

    I understand that the minimum reset pulse is 1 ms.

    Q1. Is the falling edge of GRSTz necessary at power-on?

    　　In other words, is the situation where VDD rises but GRSTz remains low as in figure.2.

    Q2. If the answer for Q1 is Yes, what is the T1to2 which is the time from the rise of the power supply to the fall of GRSTz.

           There is no power-up sequence for the power supplies VDD, VDD33, and VDDA33. What is the timing of T1?

    Q3. If the answer for Q1 is No, what is the T1to3 in Figure 2?

    Q4. The GRSTz pin is an internal pull-up. Which power supply is pulled up? VDD33 or VDDA33?

    Q5. Is there an order to shut down GRSTz when the power is turned off?

    Q6. Are there multiple blocks that are reset inside the chip?

    　　For example, when a plurality of blocks are reset, does a malfunction occur due to a timing shift of a level shifter or the like?

    　　

    Best regards,

    Tomoaki Yoshida

    　　

  • 0 in reply to Tomoaki Yoshida91
    TI__Guru**** 158955 points

    Q1: both are works as long Treset is over 1ms, but prefer figure 2

    Q2: /Q3: as long as T3-T2 is over 1ms, T2-T1 is not important

    Q4 VDD33

    Q5: no order for GRST and power

    Q6: only one reset for this device

  • 0 in reply to Brian Zhou
    Genius 5255 points

    Hi Brian-san,

    Thank your for your answer.

    The following is your answer : "Q2: /Q3: as long as T3-T2 is over 1ms, T2-T1 is not important".

    At this time, what timing should the reset pulse start be considered?

    I understand that VDD33, VDDA33 and VDD power supply start order is not restricted.

    GRSTz is pulled up to VDD33, so should only the rising up of VDD33 be considered a start?

    Please see the attached.

    I want to know if such a case is allowed, that is, the condition of T1 in this figure.

    The following is your answer :"Q6: only one reset for this device"

    Dose this meas that only one circuit block inside the chip is reset?

    Could you tell me what kind of circuit block?

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    TI__Guru**** 158955 points

    T1 should be the last power supply get ready.

    GRST means global reset, it rest the whole chip.

  • 0 in reply to Brian Zhou
    Genius 5255 points

    Hi Brian-san,

    Thank you for your support.

    >T1 should be the last power supply get ready.

    I understand.

    >GRST means global reset, it rest the whole chip.

    Since the whole chip is reset, there is no possibility of malfunction?

    Does unexpected operation occur when a short reset pulse of 1 ms or less is input?

    Or is this short pulse ignored?

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    TI__Guru**** 158955 points

    when a short reset pulse of 1 ms or less, device may not reset correctly and unexpected operation occur

  • 0 in reply to Brian Zhou
    Genius 5255 points

    Hi Brian-san,

    Thank you for your support.

    I understand well.

    Best regards,

    Tomoaki Yoshida