• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 33 subscribers
  • Views 303 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS160PR410: Long length trace limitation, is clock need to be conditioning ?

Oliver Lin
Expert 4475 points
Part Number: DS160PR410
Other Parts Discussed in Thread: LMK00334

Hi team,

Customer has a mother board design with 11000mils, on the dock with 3000mils. Still need to add a cable length.

Due to this is a long length and we found our redriver has data conditioning but clock signal is not included. Want to know why clock conditioning is not required.

Regards,

Oliver

  • 0
    TI__Mastermind 43795 points

    Hi Oliver,

    It will be necessary to buffer the clock for extreme PCIe trace lengths (or attenuation).  The PCIe Base Specification lists the clock trace attenuation for the electrical testing limits as -15dB @ 4 GHz.  Placing the clock generation in a "central" location between RC and EP locations should allow for buffer free common clock architecture in most systems.

    Regards,

    Lee 

  • 0 in reply to Lee Sledjeski
    TI__Expert 4475 points

    Hi Lee,

    Thank you for your suggestion, do you have any suggestion circuit or device for the clock buffer? Due to customer design is NB connects to a dock via type C. Where the clock gen should be placed?

  • 0 in reply to Oliver Lin
    TI__Mastermind 43795 points

    Hi Oliver,

    Sorry for the delay.  The clock buffer we have been using for PCIe Gen3 and Gen4 applications is the LMK00334 device.

    I would try to place it closer to the type C connector going to the dock. 

    Regards,

    Lee