SN65DSI83: Register settings configuration in SN65SDI83 for the Test Pattern

Rajat Barmon1

Part Number: SN65DSI83
Other Parts Discussed in Thread: DSI-TUNER

Dear All,

I am Rajat Barmon.I am working in a company in Germany. Recently, I am doing a project which is related with SN65DSI83 Evaluation board (MIPI to LVDS Interface).

I was using Tianma dsiplay (TM101JVHG32) display for the test pattern.Somehow it is not working Because of the right register settings. (Ref. clock : 65MHz, I am not using DSI clock).This is the Right test Pattern for this SN65DSI83 board.

2. This is my Register settings for SN65DSI83 which I made.

I did not get the any color into the display. Can you help me where is going to wrong in my settings.This is my Hardware Setup.

Backlight is on.But the display is not working. PLL is not locked anyways. So, I can not go further before lock teh PLL. Can you help me regarding the problem how I will get the right register settings and work correctly. Thank You.

Regards,

Rajat Barmon

over 4 years ago

0 Rajat Barmon1 over 4 years ago

Intellectual 350 points

This is the Test Pattern.

DSI Tuner configuration.

These are the register settings which I made

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Did you enable the PLL by writing 0x01 to register 0x0D after configuring the rest of the registers? The output file from the DSI-Tuner does not enable the PLL because the user needs to do this manually.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Hello I.K,

Thank you for your reply. I am getting completely wrong value to the register. Please see the screenshoot below:

Yes I configured the 0x0D=0x01.

Can you help me regarding this issue ? I am waiting for your reply.

Regards,

Rajat Barmon

0 Rajat Barmon1 over 4 years ago in reply to Rajat Barmon1

Intellectual 350 points

Hello I.K,

Thank you for your reply. I am getting completely wrong value to the register. Please see the screenshoot below:

Yes I configured the 0x0D=0x01.

Can you help me regarding this issue ? I am waiting for your reply.

Regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

There must be something wrong with your code because your register dump is not reflecting your settings. For example, 0x0A (a clock register) reads 0x00 when it should read 0x04 according to your settings. Same with register 0x12, 0x0D, etc. Please investigate your code.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Here is my code, If you have some time,Can you check it where is the problem in my code ?

Thank you,

Best regards,

Rajat Barmon

/*******************************************************************************
* @FILE: SN65DSI83.c
* @Brief: SN65DSI83 driving source file
* SN65DSI83 MIPI to LVDS Bridge
*
*******************************************************************************/
/* */
/* Projekt: . */
/* Modul: SN65DSI83.c */
/* Bearbeiter: Hinderegger */
/* Begonnen: Februar 2020 */
/* Controller: Cygnal C8051F380 */
/* Platine: Mango12 Front PCB 27.013.01 */
/* akt. Stand: 14.02.2020 */
/* */
/******************************************************************************/

/*============================================================================
Include files
============================================================================*/
#include <stdio.h>

#include "..\inc\cpu.h"
#include "..\inc\USB_Main.h"
#include "..\inc\SN65DSI83.h"
#include "..\inc\sio0.h"
#include "..\inc\iic.h"
#include "..\inc\spaxt.h"
#include "..\inc\utils.h"

/*============================================================================
Definitions
============================================================================*/
#define _SN65DSI83_REG_

/*============================================================================
Global variable definitions
============================================================================*/

// extern
extern bit bSN65DSI83 ;

#ifdef _SN65DSI83_REG_
//=====================================================================
// Filename : CSR-auo-G104XVN10-68MHz.txt
// AUO G104XVN01 WXGA 1024x768
//
// (C) Copyright 2013 by Texas Instruments Incorporated.
// All rights reserved.
//
/* ====================================================================
// Filename : CSR-auo-G104XVN10-68MHz.txt
#define _LVDS_TEST_PATTERN_
#define SN65_NUM_WRITABLE_REG 43

// Filename : CSR-auo-G104XVN10-65MHz.txt
#define _LVDS_TEST_PATTERN_
#define SN65_NUM_WRITABLE_REG 43

SEG_XDATA U8 SN65_defaultConfiguration [SN65_NUM_WRITABLE_REG] [2] =
{ // Address, Value
// Reset and Clock Registers
{ 0x09, 0x00 }, // 01
{ 0x0A, 0x04 }, // 02
{ 0x0B, 0x00}, // 03 0x00= LVDS clock = source clock (default) / 0x01: == RefClk * 2
{ 0x0D, 0x00 }, //0x01 }, // 04
// DSI Registers
{ 0x10, 0x26 }, // 0x36 }, // 05
{ 0x11, 0x00 }, // 06
{ 0x12, 0x1D }, // 0x3A }, // 07
{ 0x13, 0x00 }, // 08
// LVDS Registers
//{ 0x18, 0xF0 }, // 09 xF0 / 0x72: DE negativ, HS
//{ 0x18, 0x70 }, // 09 xF0 / 0x72: DE negativ, HS -> Farben falsch rot beginnt richtig
{ 0x18, 0x78}, // 09 xF0 / DE positiv!?
// LVDS_LINK_CFG(CSR 0x18.4) = 1b
// 0xF0: DE negaiv polarity (activ->0); HS is negative polarity; VS is negative polarity
// Force 18bpp; CHA Format 2
// 0xF2: DE negaiv polarity (activ->0); HS is negative polarity; VS is negative polarity
// Force 18bpp; CHA Format 1
// 0x72: DE positiv (activ->1); HS is negative polarity; VS is negative polarity
// Force 18bpp; CHA Format 1
{ 0x19, 0x00 }, // 10
{ 0x1A, 0x03 }, // 11 0x03
{ 0x1B, 0x00 }, // 12
// Video Registers
{ 0x20, 0x00 }, // 13
{ 0x21, 0x05 }, // 14 CHA Resolution 0x21+0x20 = 0x0400 = 1024
{ 0x22, 0x00 }, // 15
{ 0x23, 0x00 }, // 16
{ 0x24, 0x20 }, // 17
{ 0x25, 0x03 }, // 18 CHA Resolution 0x24+0x25 = 0x0300 = 768
{ 0x26, 0x00 }, // 19
{ 0x27, 0x00 }, // 20
{ 0x28, 0x20 }, // 21
{ 0x29, 0x00 }, // 22 CHA 0x29 + 0x28 Sync delay
{ 0x2A, 0x00 }, // 23
{ 0x2B, 0x00 }, // 24
// CHA_HSYNC_PULS_WIDTH
{ 0x2C, 0x01 }, // x19 0x27 }, // 25
{ 0x2D, 0x00 }, // 26 bei 0x01 Abnzeige verschoben ?!?!?
// CHA_HSYNC_PULS_WIDTH 2C u. 2D
//{ 0x2C, 0x2c }, // x19 0x27 }, // 25
//{ 0x2D, 0x01 }, // 26 bei 0x01 Abnzeige verschoben ?!?!?
{ 0x2E, 0x00 }, // 27
{ 0x2F, 0x00 }, // 28
// CHA_VSYNC_PULS_WIDTH x30 u. x31
{ 0x30, 0x01 }, // 29
{ 0x31, 0x00 }, // 30
{ 0x32, 0x00 }, // 31
{ 0x33, 0x00 }, // 32
// CHA_HSYNC_HORIZONTAL_BACK_PORCH x34
//{ 0x34, 0x010 }, // 0xdc }, x1c // 33
//{ 0x35, 0x01 }, // 34 x01
{ 0x34, 0x04 }, // 0xdc }, x1c // 33
{ 0x35, 0x00 }, // 34 x01
{ 0x36, 0x01 }, // 35
{ 0x37, 0x00 }, // 36
// CHA_HSYNC_HORIZONTAL_FRONT_PORCH x38,x39
// { 0x38, 0x2B }, // 0x3C }, // 37
// { 0x39, 0x01 }, // 38
{ 0x38, 0x40 }, // 0x3C }, // 37
{ 0x39, 0x00 }, // 38
// CHA_VERTICAL_FRONT_PORCH x3A
{ 0x3A, 0x28 }, // 39
{ 0x3B, 0x00 }, // 40
#ifdef _LVDS_TEST_PATTERN_
{ 0x3C, 0x10 }, // 41 CHA_TEST_PATTERN (0x10)
#else
{ 0x3C, 0x00 }, //
#endif // _LVDS_TEST_PATTERN_
{ 0x3D, 0x00 }, // 42
{ 0x3E, 0x00 } // 43
};

// The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the
// recommended sequence defined in the datasheet

#endif // _SN65DSI83_REG_

#ifdef _SN65DSI83_POR_
/*
SEG_XDATA U8 SN65_defaultConfiguration [SN65_NUM_WRITABLE_REG] [2] =
{ // Address, Value
{ 0x09, 0x00 }, // 01
{ 0x0A, 0x05 }, // 02
{ 0x0B, 0x10 }, // 03
{ 0x0D, 0x00 }, // 04
{ 0x10, 0x2e }, // 05
{ 0x11, 0x00 }, // 06
{ 0x12, 0x28 }, // 07
{ 0x13, 0x00 }, // 08
{ 0x18, 0x72 }, // 09
{ 0x19, 0x00 }, // 10
{ 0x1A, 0x03 }, // 11
{ 0x1B, 0x00 }, // 12
{ 0x20, 0x00 }, // 13
{ 0x21, 0x05 }, // 14
{ 0x22, 0x00 }, // 15
{ 0x23, 0x00 }, // 16
{ 0x24, 0x00 }, // 17
{ 0x25, 0x00 }, // 18
{ 0x26, 0x00 }, // 19
{ 0x27, 0x00 }, // 20
{ 0x28, 0xcf }, // 21
{ 0x29, 0x01 }, // 22
{ 0x2A, 0x00 }, // 23
{ 0x2B, 0x00 }, // 24
{ 0x2C, 0x01 }, // 25
{ 0x2D, 0x00 }, // 26
{ 0x2E, 0x00 }, // 27
{ 0x2F, 0x00 }, // 28
{ 0x30, 0x01 }, // 29
{ 0x31, 0x00 }, // 30
{ 0x32, 0x00 }, // 31
{ 0x33, 0x00 }, // 32
{ 0x34, 0x05 }, // 33
{ 0x35, 0x00 }, // 34
{ 0x36, 0x00 }, // 35
{ 0x37, 0x00 }, // 36
{ 0x38, 0x00 }, // 37
{ 0x39, 0x00 }, // 38
{ 0x3A, 0x00 }, // 39
{ 0x3B, 0x00 }, // 40
{ 0x3C, 0x00 }, // 41
{ 0x3D, 0x00 }, // 42
{ 0x3E, 0x00 } // 43
};

*/
/* -------------------------------------
SN65DSI83 POR Default:
Reg 0x09=0x00
Reg 0x0A=0x0A
Reg 0x0B=0x00
Reg 0x0D=0x00
Reg 0x10=0x3E
Reg 0x11=0x00
Reg 0x12=0x00
Reg 0x13=0x00
Reg 0x18=0x70
Reg 0x19=0x05
Reg 0x1A=0x03
Reg 0x1B=0x00
Reg 0x20=0x00
Reg 0x21=0x00
Reg 0x22=0x00
Reg 0x23=0x00
Reg 0x24=0x00
Reg 0x25=0x00
Reg 0x26=0x00
Reg 0x27=0x00
Reg 0x28=0x00
Reg 0x29=0x00
Reg 0x2A=0x00
Reg 0x2B=0x00
Reg 0x2C=0x00
Reg 0x2D=0x00
Reg 0x2E=0x00
Reg 0x2F=0x00
Reg 0x30=0x00
Reg 0x31=0x00
Reg 0x32=0x00
Reg 0x33=0x00
Reg 0x34=0x00
Reg 0x35=0x00
Reg 0x36=0x00
Reg 0x37=0x00
Reg 0x38=0x00
Reg 0x39=0x00
Reg 0x3A=0x00
Reg 0x3B=0x00
Reg 0x3C=0x00
Reg 0x3D=0x00
Reg 0x3E=0x00
------------------------------------- */
#endif // _SN65DSI83_POR_

/*============================================================================
Prototype definitions
============================================================================*/

U8 readSN65Register (U8 I2Creg) ;

// extern

/*============================================================================
Function Definitions
============================================================================*/

/*============================================================================
Name : readSN65Register()
------------------------------------------------------------------------------
@brief Reads a 8 bit value from the specified SN65DSI83 register

@Input: I2C Register Nummer
@Output: none
@Return: 1 Byte Register value
@Notes: none
============================================================================*/

U8 readSN65Register (U8 I2Creg) {
register U8 value ;

SM_Send (SN65DSI83_SLAVE_ADDR, I2Creg) ; // IIC Adresse setzen
value = SM_Receive (SN65DSI83_SLAVE_ADDR, READ_1_BYTE) ;
return ( value ) ;
}

/*void writeSN65Register (U8 I2Creg, U8 value) {

SM_Send_2B (SN65DSI83_SLAVE_ADDR, I2Creg, value) ; // IIC Adresse setzen
}*/

/*============================================================================
Name : printSN65Register ()
------------------------------------------------------------------------------
@brief SN65DSI83 Regsiter aulesen und ausgeben..
Default Register ermittelt mit TI DSI-Tuner
siehe: CSR-Tianma-TM101JVHG32-01.txt
@Input: ucMode
@Output: none
@Return: none
@Notes: none
============================================================================*/

void printSN65Register (void) {

#ifdef _SN65DSI83_REG_
SEG_XDATA U8 i ;
SEG_XDATA U8 iReg ;
SEG_XDATA U16 iVal ;
SEG_XDATA U8 ucTmp[6] ;

putstr (TRENNLINIE);
putstr ("SN65DSI83 Register\r");

for (i = 0; i < SN65_NUM_WRITABLE_REG; i++)
{
iReg = SN65_defaultConfiguration[i] [0] ;
iVal = readSN65Register (iReg) ;

putstr ("Reg 0x") ;
put2Hex2Buffer (ucTmp, iReg) ;
putstr (ucTmp);
putstr ("= 0x") ;
put2Hex2Buffer (ucTmp, (U8) (iVal)) ;
putstr (ucTmp);
putstr ("\r");
}
putstr (TRENNLINIE);
#endif // _SN65DSI83_REG_
}

/*============================================================================
Name : setSN65Register ()
------------------------------------------------------------------------------
@brief .
@Input: ucMode
@Output: none
@Return: none
@Notes: none
============================================================================*/
void setSN65Register (U8 ucMode) {
SEG_XDATA U8 i ;
SEG_XDATA U8 uReg ;
SEG_XDATA U8 uVal ;
SEG_XDATA U8 ucTmp[6] ;

if (ucMode > 0) {
putstr ("set SN65DSI83 Register: ");

// set SOFT_RESET bit to 1
// Eintrag 00=Reg 0x09
//uReg = SN65_defaultConfiguration [0x00] [0] ;
//uVal = SN65_defaultConfiguration [0x00] [1] ;
//uVal |= 0x01 ;
//SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ; // IIC Adresse setzen

// delay_ms (SPAXT_20MSEK) ;

// set PLL_EN bit to 0: Reg 0x0D.0 = 0 PLL disable
// Eintrag 03=Reg 0x0D

uReg = SN65_defaultConfiguration [0x03] [0] ; // reg nr
uVal = SN65_defaultConfiguration [0x03] [1] ; // re value
uVal &= 0xFE ;
SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ; // IIC Adresse setzen
delay_ms (SPAXT_20MSEK) ;

// min. 3ms warten
//delay_ms (SPAXT_10MSEK) ;

for (i = 1; i < SN65_NUM_WRITABLE_REG; i++)
{
uReg = SN65_defaultConfiguration [i] [0] ;
uVal = SN65_defaultConfiguration [i] [1] ;
//writeSN65Register (uReg, uVal) ;
SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ; // IIC Adresse setzen
}
putstr ("..done.\r");

printSN65Register () ;

// min. 3ms warten
delay_ms (SPAXT_10MSEK) ;

// The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the
// recommended sequence defined in the datasheet

// set PLL_EN bit to 1: Reg 0x0D.0 = 1
// Eintrag 03=Reg 0x0D
uReg = SN65_defaultConfiguration [0x03] [0] ;
uVal = SN65_defaultConfiguration [0x03] [1] ;
uVal |= 0x01 ;
SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ; // IIC Adresse setzen
// min. 3ms warten
delay_ms (SPAXT_10MSEK) ;

// set SOFT_RESET bit to 1
// Eintrag 00=Reg 0x09
uReg = SN65_defaultConfiguration [0x00] [0] ;
uVal = SN65_defaultConfiguration [0x00] [1] ;
uVal |= 0x01 ;
SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ; // IIC Adresse setzen
delay_ms (SPAXT_10MSEK) ;

// clear Error Register
#define ERROR_REG 0xE5
SM_Send_2B (SN65DSI83_SLAVE_ADDR, ERROR_REG, 0xFF) ;// IIC Adresse setzen

delay_ms (SPAXT_2MSEK) ; //delay 2 ms
// read error Register
uReg = ERROR_REG ;
uVal = readSN65Register (uReg) ;
//printSN65Register
putstr ("Error Reg 0x") ;
put2Hex2Buffer (ucTmp, uReg) ;
putstr (ucTmp);
putstr ("= 0x") ;
put2Hex2Buffer (ucTmp, uVal) ;
putstr (ucTmp);
putstr ("\r");
}
}

/*============================================================================
Name : eeeT()
------------------------------------------------------------------------------
@brief .
@Input: none
@Output: none
@Return: none
@Notes: none
============================================================================*/
/*void eeeT (void) {

}*/

/*============================================================================
END OF FILE
============================================================================*/

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Sorry but I cannot help with checking your code. I can only help with the DSI83 register settings and configuration.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Then please help me with register settings

regards,

Rajat

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

You will need to fix your code so that the register dump reflects what you are trying to write to the registers before I can help you with your settings.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Hello I.K,

May be due to initial sequence is not correct. How i will EN pin to high manually ? I am struggling this problem. Please help me.

I am waiting for your reply.

Regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

To assert the EN pin high manually you just need to apply 1.8V to it. However, you need to ensure that it's enabled in accordance with the initialization sequence. This FAQ has an example of what the initialization sequence should look like on an oscilloscope: https://e2e.ti.com/support/interface/f/138/t/852871?-FAQ-SN65DSI84-No-display-output-with-SN65DSI83-SN65DSI84-SN65DSI85

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.K,

The initial sequence is right. but the PLL is not locked when the reference clock is 65Mhz. can you tell me how i can resolve the problem ?

Reagrds,

Rajat

0 Rajat Barmon1 over 4 years ago in reply to Rajat Barmon1

Intellectual 350 points

Dear I.K,

When Press 's' PLL locked and read the register value.

After that, when press 't' for set the clock then nothing is displayed as before and PLL aslo not locked in this situation.

Now the problem is why PLL is not locked when we set the reference clock ? do you have any idea ?

I am waiting for your reply.

Best regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Can you export and send me the .dsi file from the DSI-Tuner with your settings (press Ctrl+E in the DSI-Tuner)?

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.k,

Thank you for your reply. .dsi file is not supporting. Hence, I attached screen shoot. Please see the file. Or if you give me your email address then i can send to you email address.

I am waiting for you reply,

Reagrds,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

There are a couple of things wrong with those settings:

1. You have the bits per pixel on the Panel Inputs as 24bpp, but the DSI video mode as RGB666packed in the DSI_Inputs window

2. The pixel/line parameters on the Panel Inputs window do not match the parameters in the DSI_Inputs window

Please watch this training video and correct the settings: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-single-link-lvds-operation

Also, for the PLL not locking, check the following:

1. Since you're using a reference clock, make sure the clock frequency is exactly 65 MHz as indicated by your settings

2. Make sure you're enabling the PLL in accordance with the initialization sequence

Additionally, you need to ensure that your DSI source output matches exactly with whatever settings you put into the DSI_Inputs window (clock frequency, video mode, pixel/line parameters, etc.)

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.k,

Thank you for your reply.

I am not using DSI Clock. Hence, do i need to set the parameter for DSI Input ?

I am using 65Mhz and also getting 65Mhz on the board (R104). But display is not coming .

REF_CLK_65MHz.txt

	{ 0x00, 0x01 },		// 01: 
									//    bit 7: E_EL Device identifivation. 0= CDCEL913 (1.8 V out)
									//    bit [6:4] RID Revision identification number (read-only)
									//    bit [3:0] VID Vendor identificatio nnumber (read-only) = 1
		{ 0x01, 0x01 },//0x00?		// 02: SLAVE_ADR[1:0] 01b Address bits A0 and A1 of the slavereceiveraddress0
		{ 0x02, 0xB4 },		// 03; 0xB4 = 0b1011.0100
									//    bit 7:	M1	1b	Clock source selection for output Y1:0-Inputclock / 1-PLL1clock
									//    bit 6: 	SPICON Operation mode selection for pin 12/13: 0=Serial programming interface SDA(pin 13) and SCL(pin 12)
									//    bit 5-4: Y1_ST1: Y1-State definition 11= Y1 enabled
									//    bit 3-2: Y1_ST0: Y0-State definition 01= Y0 disabled to 3-state
									//    bit 1-0: Pdiv1[9:8] 10-bitY1-output-divider Pdiv1: 00 = Divider reset and stand-by
		{ 0x03, 0x03 },		// 04
									//    bit Pdiv1[7:0] 0x01= div 1
		{ 0x04, 0x02 },		// 05 0x02 = 0b0000.0010 Y1_x State Selection
									//    bit 2: Y1_1:	1= State1(predefinedby Y1_ST1)
									//    bit 
		{ 0x05, 0x50 },		// 06 XCSEL: Crystal load capacitor selection
									//    0x50=20pF (bit[2:0] reserved)
		{ 0x06, 0x40 }, 		// 07 BCOUNT / EEWRITE 	0x0e = 0b0000.1110
									//    bit [7:1] 7-bit byte count (defines the number of bytes which will be sent from this device at the next BlockRead transfer);
									//		all bytes must be readout to finish the read cycle correctly.
									//    bit [0] EEWRITE  Initiate EEPROM write cycle -> 0= No EEPROM write cycle
		{ 16, 0x00 }, 		// 08 SSC1: PLL1 SSC selection -> 0=Spread Spectrum off
		{ 17, 0x00 }, 		// 09 SSC1: PLL1 -> 0=Spread Spectrum off
		{ 18, 0x00 }, 		// 10 SSC1: PLL1 -> 0=Spread Spectrum off
		{ 19, 0x00 }, 		// 11 FS1_x:PLL1frequencyselection
									//    all 0 -> predefined by PLL1_0 - multiplier/divider value 
		{ 20, 0x6d }, 		// 12 PLL Multiplexer 0xED = 0b1110.1101
									//    bit 7: MUX1 PLL1 multiplexer: 1-> PLL1 bypass
									//    bit 6: M2 Output Y2 multiplexer 1-> Pdiv2
									//    bit [5:4]: M3 Output Y3 multiplexer 10->
									//    bit [3:2]: Y2Y3_ST1 11-> Y2/Y3 enabled
									//    bit [1:0]: Y2Y3_ST0 01-> Y2/Y3 disabled to 3-State
		{ 21, 0x02 }, 		// 13 Y2Y3_x output state selection 0x02 = 0b0000.0010
									//    bit 2: 1= State1 (predefined by Y2Y3_ST1)  
		{ 22, 0x00 }, 		// 14 Pdiv2 1= div 1
		{ 23, 0x00 }, 		// 15 Pdiv3 1= div 1
		{ 24, 0xE3 }, 		// 16 
									//    bit [7:0] PLL1_0N [11:4]
		{ 25, 0x8E }, 		// 17 
									//    bit [7:4] PLL1_0N [3:0]
									//    bit [3:0] PLL1_0R [8:5]
		{ 26, 0x03 }, 		// 18 
									//    bit [7:3] PLL1_0R [4:0]
									//    bit [2:0] PLL1_0Q [5:3]
/*27*/{ 27, 0x8B }, 		// 19 
									//    bit [7:5] PLL1_0Q [2:0]
									//    bit [4:2] PLL1_0P [2:0]
									//    bit [1:0]  fVCO1_0 range selection: 00 - fVCO1_1 < 125 MHz
		{ 28, 0xE3 }, 		// 20 
									//    bit [7:0] PLL1_1N [11:4]
		{ 29, 0x8E }, 		// 21 
									//    bit [7:4] PLL1_1N [3:0]
									//    bit [3:0] PLL1_1R [8:5]
		{ 30, 0x03 }, 		// 22 PLL1_1
									//    bit [7:3] PLL1_1R [4:0]
									//    bit [2:0] PLL1_1Q [5:3]
/*31*/{ 31, 0x88 } 		// 23
									//    bit [7:5] PLL1_1Q [2:0]
									//    bit [4:2] PLL1_1P [2:0]
									//    bit [1:0]  fVCO1_1 range selection: 00 - fVCO1_1 < 125 MHz
	};

SN65DSI83.txt

                   /*******************************************************************************
*   @FILE:  SN65DSI83.c
*   @Brief: SN65DSI83 driving source file
*   SN65DSI83 MIPI to LVDS Bridge 
*   
*******************************************************************************/
/*																										*/
/* Projekt:			.																				*/
/* Modul:			SN65DSI83.c																	*/
/* Bearbeiter:		Hinderegger																	*/
/* Begonnen:      Februar 2020																*/
/* Controller:		Cygnal C8051F380															*/
/* Platine: 		Mango12 Front PCB 27.013.01											*/
/* akt. Stand:		14.02.2020																	*/
/*																										*/
/******************************************************************************/

/*============================================================================
Include files
============================================================================*/
#include <stdio.h>

#include "..\inc\cpu.h"
#include "..\inc\USB_Main.h"
#include "..\inc\SN65DSI83.h"
#include "..\inc\sio0.h"
#include "..\inc\iic.h"
#include "..\inc\spaxt.h"
#include "..\inc\utils.h"

/*============================================================================
Definitions
============================================================================*/
#define _SN65DSI83_REG_

/*============================================================================
Global variable definitions
============================================================================*/

// extern
extern bit bSN65DSI83 ;


#ifdef _SN65DSI83_REG_
//=====================================================================
// Filename   : CSR-auo-G104XVN10-68MHz.txt
//		AUO G104XVN01 WXGA 1024x768
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
/* ====================================================================
// Filename   : CSR-auo-G104XVN10-68MHz.txt
	#define _LVDS_TEST_PATTERN_
	#define SN65_NUM_WRITABLE_REG 43

*/

// Filename   : CSR-auo-G104XVN10-65MHz.txt
	#define _LVDS_TEST_PATTERN_
	#define SN65_NUM_WRITABLE_REG 43

	SEG_XDATA U8 SN65_defaultConfiguration [SN65_NUM_WRITABLE_REG] [2] =   
	{	//  Address, Value
			// Reset and Clock Registers
		{ 0x09, 0x00 },		// 01
		{ 0x0A, 0x04 },		// 02
		{ 0x0B, 0x00},		// 03 0x00= LVDS clock = source clock (default) / 0x01: == RefClk * 2
		{ 0x0D, 0x00 },	//0x01 },		// 04
			// DSI Registers
		{ 0x10, 0x26 }, // 0x36 },		// 05
		{ 0x11, 0x00 },		// 06
		{ 0x12, 0x1D }, // 0x3A },		// 07
		{ 0x13, 0x00 },		// 08
			// LVDS Registers
		//{ 0x18, 0xF0 },		// 09 xF0 / 0x72: DE negativ, HS
		//{ 0x18, 0x70 },		// 09 xF0 / 0x72: DE negativ, HS -> Farben falsch rot beginnt richtig
		{ 0x18, 0x78},		// 09 xF0 / DE positiv!?
				// LVDS_LINK_CFG(CSR 0x18.4) = 1b
				// 0xF0: DE negaiv polarity (activ->0); HS is negative polarity; VS is negative polarity
				//			Force 18bpp; CHA Format 2
				// 0xF2: DE negaiv polarity (activ->0); HS is negative polarity; VS is negative polarity
				//			Force 18bpp; CHA Format 1
				// 0x72: DE positiv (activ->1); HS is negative polarity; VS is negative polarity
				//			Force 18bpp; CHA Format 1
		{ 0x19, 0x00 },		// 10
		{ 0x1A, 0x03 },		// 11 0x03
		{ 0x1B, 0x00 },		// 12 
			// Video Registers
		{ 0x20, 0x00 },		// 13
		{ 0x21, 0x05 },		// 14 CHA Resolution 0x21+0x20 = 0x0400 = 1024
		{ 0x22, 0x00 },		// 15
		{ 0x23, 0x00 },		// 16
		{ 0x24, 0x20 },		// 17
		{ 0x25, 0x03 },		// 18 CHA Resolution 0x24+0x25 = 0x0300 = 768
		{ 0x26, 0x00 },		// 19
		{ 0x27, 0x00 },		// 20
		{ 0x28, 0x20 },		// 21
		{ 0x29, 0x00 },		// 22 CHA 0x29 + 0x28 Sync delay
		{ 0x2A, 0x00 },		// 23
		{ 0x2B, 0x00 },		// 24
			// CHA_HSYNC_PULS_WIDTH 
		{ 0x2C, 0x01 }, // x19 0x27 },		// 25
		{ 0x2D, 0x00 },		// 26 bei 0x01 Abnzeige verschoben ?!?!?
			// CHA_HSYNC_PULS_WIDTH 2C u. 2D
		//{ 0x2C, 0x2c }, // x19 0x27 },		// 25
		//{ 0x2D, 0x01 },		// 26 bei 0x01 Abnzeige verschoben ?!?!?
		{ 0x2E, 0x00 },		// 27
		{ 0x2F, 0x00 },		// 28
			// CHA_VSYNC_PULS_WIDTH x30 u. x31
		{ 0x30, 0x01 },		// 29
		{ 0x31, 0x00 },		// 30
		{ 0x32, 0x00 },		// 31
		{ 0x33, 0x00 },		// 32
			// CHA_HSYNC_HORIZONTAL_BACK_PORCH x34
		//{ 0x34, 0x010 }, // 0xdc },	x1c	// 33
		//{ 0x35, 0x01 },		// 34 x01
		{ 0x34, 0x04 }, // 0xdc },	x1c	// 33
		{ 0x35, 0x00 },		// 34 x01
		{ 0x36, 0x01 },		// 35
		{ 0x37, 0x00 },		// 36
			// CHA_HSYNC_HORIZONTAL_FRONT_PORCH x38,x39
			// { 0x38, 0x2B }, // 0x3C },		// 37
			// { 0x39, 0x01 },		// 38
		{ 0x38, 0x40 }, // 0x3C },		// 37
		{ 0x39, 0x00 },		// 38
			// CHA_VERTICAL_FRONT_PORCH x3A
		{ 0x3A, 0x28 },		// 39
		{ 0x3B, 0x00 },		// 40
#ifdef _LVDS_TEST_PATTERN_
		{ 0x3C, 0x10 },		// 41	CHA_TEST_PATTERN (0x10)
#else
		{ 0x3C, 0x00 },		// 
#endif	// _LVDS_TEST_PATTERN_
		{ 0x3D, 0x00 },		// 42
		{ 0x3E, 0x00 }    	// 43
	};

	// The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the 
	// recommended sequence defined in the datasheet

#endif	// _SN65DSI83_REG_




#ifdef _SN65DSI83_POR_
/*	
	SEG_XDATA U8 SN65_defaultConfiguration [SN65_NUM_WRITABLE_REG] [2] =   
	{	//  Address, Value
		{ 0x09, 0x00 },		// 01
		{ 0x0A, 0x05 },		// 02
		{ 0x0B, 0x10 },		// 03
		{ 0x0D, 0x00 },		// 04
		{ 0x10, 0x2e },		// 05
		{ 0x11, 0x00 },		// 06
		{ 0x12, 0x28 },		// 07
		{ 0x13, 0x00 },		// 08
		{ 0x18, 0x72 },		// 09
		{ 0x19, 0x00 },		// 10
		{ 0x1A, 0x03 },		// 11
		{ 0x1B, 0x00 },		// 12
		{ 0x20, 0x00 },		// 13
		{ 0x21, 0x05 },		// 14
		{ 0x22, 0x00 },		// 15
		{ 0x23, 0x00 },		// 16
		{ 0x24, 0x00 },		// 17
		{ 0x25, 0x00 },		// 18
		{ 0x26, 0x00 },		// 19
		{ 0x27, 0x00 },		// 20
		{ 0x28, 0xcf },		// 21
		{ 0x29, 0x01 },		// 22
		{ 0x2A, 0x00 },		// 23
		{ 0x2B, 0x00 },		// 24
		{ 0x2C, 0x01 },		// 25
		{ 0x2D, 0x00 },		// 26
		{ 0x2E, 0x00 },		// 27
		{ 0x2F, 0x00 },		// 28
		{ 0x30, 0x01 },		// 29
		{ 0x31, 0x00 },		// 30
		{ 0x32, 0x00 },		// 31
		{ 0x33, 0x00 },		// 32
		{ 0x34, 0x05 },		// 33
		{ 0x35, 0x00 },		// 34
		{ 0x36, 0x00 },		// 35
		{ 0x37, 0x00 },		// 36
		{ 0x38, 0x00 },		// 37
		{ 0x39, 0x00 },		// 38
		{ 0x3A, 0x00 },		// 39
		{ 0x3B, 0x00 },		// 40
		{ 0x3C, 0x00 },		// 41
		{ 0x3D, 0x00 },		// 42
		{ 0x3E, 0x00 }    	// 43
	};

*/
		/* ------------------------------------- 
		SN65DSI83 POR Default:
		Reg 0x09=0x00
		Reg 0x0A=0x0A
		Reg 0x0B=0x00
		Reg 0x0D=0x00
		Reg 0x10=0x3E
		Reg 0x11=0x00
		Reg 0x12=0x00
		Reg 0x13=0x00
		Reg 0x18=0x70
		Reg 0x19=0x05
		Reg 0x1A=0x03
		Reg 0x1B=0x00
		Reg 0x20=0x00
		Reg 0x21=0x00
		Reg 0x22=0x00
		Reg 0x23=0x00
		Reg 0x24=0x00
		Reg 0x25=0x00
		Reg 0x26=0x00
		Reg 0x27=0x00
		Reg 0x28=0x00
		Reg 0x29=0x00
		Reg 0x2A=0x00
		Reg 0x2B=0x00
		Reg 0x2C=0x00
		Reg 0x2D=0x00
		Reg 0x2E=0x00
		Reg 0x2F=0x00
		Reg 0x30=0x00
		Reg 0x31=0x00
		Reg 0x32=0x00
		Reg 0x33=0x00
		Reg 0x34=0x00
		Reg 0x35=0x00
		Reg 0x36=0x00
		Reg 0x37=0x00
		Reg 0x38=0x00
		Reg 0x39=0x00
		Reg 0x3A=0x00
		Reg 0x3B=0x00
		Reg 0x3C=0x00
		Reg 0x3D=0x00
		Reg 0x3E=0x00
		------------------------------------- */
#endif // _SN65DSI83_POR_

/*============================================================================
Prototype definitions
============================================================================*/


U8 readSN65Register (U8 I2Creg) ;

// extern


/*============================================================================
Function Definitions
============================================================================*/

/*============================================================================
Name	:   readSN65Register()
------------------------------------------------------------------------------
@brief  Reads a 8 bit value from the specified SN65DSI83 register
			
@Input:	I2C Register Nummer
@Output:	none
@Return: 1 Byte Register value
@Notes:	none
============================================================================*/

U8 readSN65Register (U8 I2Creg) {
	register U8 value ;

	SM_Send (SN65DSI83_SLAVE_ADDR, I2Creg) ;	// IIC Adresse setzen
	value = SM_Receive (SN65DSI83_SLAVE_ADDR, READ_1_BYTE) ;
	return ( value ) ;
}

/*============================================================================
Name	:   readSN65Register()
------------------------------------------------------------------------------
@brief  Reads a 8 bit value from the specified SN65DSI83 register
			
@Input:	I2C Register Nummer
@Output:	none
@Return: 1 Byte Register value
@Notes:	none
============================================================================*/

/*void writeSN65Register (U8 I2Creg, U8 value) {

	SM_Send_2B (SN65DSI83_SLAVE_ADDR, I2Creg, value) ;	// IIC Adresse setzen
}*/

/*============================================================================
Name	:   printSN65Register ()
------------------------------------------------------------------------------
@brief  SN65DSI83 Regsiter aulesen und ausgeben..
 Default Register ermittelt mit TI DSI-Tuner 
 siehe: CSR-Tianma-TM101JVHG32-01.txt
@Input:	ucMode
@Output:	none
@Return:	none
@Notes:	none
============================================================================*/

void printSN65Register (void) {

#ifdef _SN65DSI83_REG_
	SEG_XDATA U8 i ;	
	SEG_XDATA U8 iReg ;
	SEG_XDATA U16 iVal ;
	SEG_XDATA U8 ucTmp[6] ;

	putstr (TRENNLINIE);
	putstr ("SN65DSI83 Register\r");
	 
	for (i = 0; i < SN65_NUM_WRITABLE_REG; i++)
	{ 
		iReg = SN65_defaultConfiguration[i] [0] ;
		iVal = readSN65Register (iReg) ;

		putstr ("Reg 0x") ;
		put2Hex2Buffer (ucTmp, iReg) ;
		putstr (ucTmp);
		putstr ("= 0x") ;
		put2Hex2Buffer (ucTmp, (U8) (iVal)) ;
		putstr (ucTmp);
		putstr ("\r");
	}
	putstr (TRENNLINIE);
#endif	// _SN65DSI83_REG_
}

/*============================================================================
Name	:   setSN65Register ()
------------------------------------------------------------------------------
@brief  .
@Input:	ucMode
@Output:	none
@Return:	none
@Notes:	none
============================================================================*/
void setSN65Register  (U8 ucMode) {
	SEG_XDATA U8 i ;	
	SEG_XDATA U8 uReg ;
	SEG_XDATA U8 uVal ;
	SEG_XDATA U8 ucTmp[6] ;

	if (ucMode > 0) 	{
		putstr ("set SN65DSI83 Register: ");

			// set SOFT_RESET bit to 1
		// Eintrag 00=Reg 0x09
		//uReg = SN65_defaultConfiguration [0x00] [0] ;
		//uVal = SN65_defaultConfiguration [0x00] [1] ;
		//uVal |= 0x01 ;
		//SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		
	//	delay_ms (SPAXT_20MSEK) ;		


		// set PLL_EN bit to 0: Reg 0x0D.0 = 0 PLL disable
		// Eintrag 03=Reg 0x0D

		uReg = SN65_defaultConfiguration [0x03] [0] ; 	// reg nr
		uVal = SN65_defaultConfiguration [0x03] [1] ;	// re value
		uVal &= 0xFE ;
		SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		delay_ms (SPAXT_20MSEK) ;


	

		// min. 3ms warten
		//delay_ms (SPAXT_10MSEK) ;

		for (i = 1; i < SN65_NUM_WRITABLE_REG; i++)
		{ 
			uReg = SN65_defaultConfiguration [i] [0] ;
			uVal = SN65_defaultConfiguration [i] [1] ;
			//writeSN65Register (uReg, uVal) ;
			SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		}
		putstr ("..done.\r");

		printSN65Register () ;

		// min. 3ms warten
		delay_ms (SPAXT_10MSEK) ;

		// The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the 
		// recommended sequence defined in the datasheet

		// set PLL_EN bit to 1: Reg 0x0D.0 = 1
		// Eintrag 03=Reg 0x0D
		uReg = SN65_defaultConfiguration [0x03] [0] ;
		uVal = SN65_defaultConfiguration [0x03] [1] ;
		uVal |= 0x01 ;
		SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		// min. 3ms warten
		delay_ms (SPAXT_10MSEK) ;

		// set SOFT_RESET bit to 1
		// Eintrag 00=Reg 0x09
		uReg = SN65_defaultConfiguration [0x00] [0] ;
		uVal = SN65_defaultConfiguration [0x00] [1] ;
		uVal |= 0x01 ;
		SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		delay_ms (SPAXT_10MSEK) ;

		// clear Error Register
		#define ERROR_REG	0xE5

		SM_Send_2B (SN65DSI83_SLAVE_ADDR, ERROR_REG, 0xFF) ;// IIC Adresse setzen
		
		delay_ms (SPAXT_2MSEK) ; //delay 2 ms	
		// read error Register
		
		uReg = ERROR_REG ;
		uVal = readSN65Register (uReg) ;
//printSN65Register 
		putstr ("Error Reg 0x") ;
		put2Hex2Buffer (ucTmp, uReg) ;
		putstr (ucTmp);
		putstr ("= 0x") ;
		put2Hex2Buffer (ucTmp, uVal) ;
		putstr (ucTmp);
		putstr ("\r");
	}	
}

/*============================================================================
Name	:   eeeT()
------------------------------------------------------------------------------
@brief  .
@Input:	none
@Output:	none
@Return:	none
@Notes:	none
============================================================================*/
/*void eeeT (void) {
	
}*/

/*============================================================================
  END OF FILE
============================================================================*/

I am following these initialization:

Here, PLL is not described ! But in the register settings 0x0A.7 and 0x0D.0 are describing PLL. But I am using 0 bit for by default . should i need to change to 1 ?

I am waiting for your reply.

Thank you.

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Can you clarify what you mean by "I am not using DSI Clock"?

Even if you're not using the DSI CLK to source the device PLL, you still need the DSI CLK to strobe in the DSI data. Please make sure the device is getting a proper DSI CLK with the correct frequency from the DSI source.

Also, PLL is described in Init seq 6 of the table you attached. As described in the table, you need to set PLL_EN bit (0x0D.0) to 1 to enable the PLL.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.k,

I attached my SH65DSI.txt file. Please see the file. where I followed the initialization process and set the register. for LVDS clock, I am using Ref. clock not the DSI clock.

for PLL emable,

// set PLL_EN bit to 0: Reg 0x0D.0 = 0 PLL disable
// Eintrag 03=Reg 0x0D

and,

Please see the code.

4705.SN65DSI83.txt

                   /*******************************************************************************
*   @FILE:  SN65DSI83.c
*   @Brief: SN65DSI83 driving source file
*   SN65DSI83 MIPI to LVDS Bridge 
*   
*******************************************************************************/
/*																										*/
/* Projekt:			.																				*/
/* Modul:			SN65DSI83.c																	*/
/* Bearbeiter:		Hinderegger																	*/
/* Begonnen:      Februar 2020																*/
/* Controller:		Cygnal C8051F380															*/
/* Platine: 		Mango12 Front PCB 27.013.01											*/
/* akt. Stand:		14.02.2020																	*/
/*																										*/
/******************************************************************************/

/*============================================================================
Include files
============================================================================*/
#include <stdio.h>

#include "..\inc\cpu.h"
#include "..\inc\USB_Main.h"
#include "..\inc\SN65DSI83.h"
#include "..\inc\sio0.h"
#include "..\inc\iic.h"
#include "..\inc\spaxt.h"
#include "..\inc\utils.h"

/*============================================================================
Definitions
============================================================================*/
#define _SN65DSI83_REG_

/*============================================================================
Global variable definitions
============================================================================*/

// extern
extern bit bSN65DSI83 ;


#ifdef _SN65DSI83_REG_
//=====================================================================
// Filename   : CSR-auo-G104XVN10-68MHz.txt
//		AUO G104XVN01 WXGA 1024x768
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
/* ====================================================================
// Filename   : CSR-auo-G104XVN10-68MHz.txt
	#define _LVDS_TEST_PATTERN_
	#define SN65_NUM_WRITABLE_REG 43

*/

// Filename   : CSR-auo-G104XVN10-65MHz.txt
	#define _LVDS_TEST_PATTERN_
	#define SN65_NUM_WRITABLE_REG 43

	SEG_XDATA U8 SN65_defaultConfiguration [SN65_NUM_WRITABLE_REG] [2] =   
	{	//  Address, Value
			// Reset and Clock Registers
		{ 0x09, 0x00 },		// 01
		{ 0x0A, 0x04 },		// 02
		{ 0x0B, 0x00},		// 03 0x00= LVDS clock = source clock (default) / 0x01: == RefClk * 2
		{ 0x0D, 0x00 },	//0x01 },		// 04
			// DSI Registers
		{ 0x10, 0x26 }, // 0x36 },		// 05
		{ 0x11, 0x00 },		// 06
		{ 0x12, 0x1D }, // 0x3A },		// 07
		{ 0x13, 0x00 },		// 08
			// LVDS Registers
		//{ 0x18, 0xF0 },		// 09 xF0 / 0x72: DE negativ, HS
		//{ 0x18, 0x70 },		// 09 xF0 / 0x72: DE negativ, HS -> Farben falsch rot beginnt richtig
		{ 0x18, 0x78},		// 09 xF0 / DE positiv!?
				// LVDS_LINK_CFG(CSR 0x18.4) = 1b
				// 0xF0: DE negaiv polarity (activ->0); HS is negative polarity; VS is negative polarity
				//			Force 18bpp; CHA Format 2
				// 0xF2: DE negaiv polarity (activ->0); HS is negative polarity; VS is negative polarity
				//			Force 18bpp; CHA Format 1
				// 0x72: DE positiv (activ->1); HS is negative polarity; VS is negative polarity
				//			Force 18bpp; CHA Format 1
		{ 0x19, 0x00 },		// 10
		{ 0x1A, 0x03 },		// 11 0x03
		{ 0x1B, 0x00 },		// 12 
			// Video Registers
		{ 0x20, 0x00 },		// 13
		{ 0x21, 0x05 },		// 14 CHA Resolution 0x21+0x20 = 0x0400 = 1024
		{ 0x22, 0x00 },		// 15
		{ 0x23, 0x00 },		// 16
		{ 0x24, 0x20 },		// 17
		{ 0x25, 0x03 },		// 18 CHA Resolution 0x24+0x25 = 0x0300 = 768
		{ 0x26, 0x00 },		// 19
		{ 0x27, 0x00 },		// 20
		{ 0x28, 0x20 },		// 21
		{ 0x29, 0x00 },		// 22 CHA 0x29 + 0x28 Sync delay
		{ 0x2A, 0x00 },		// 23
		{ 0x2B, 0x00 },		// 24
			// CHA_HSYNC_PULS_WIDTH 
		{ 0x2C, 0x01 }, // x19 0x27 },		// 25
		{ 0x2D, 0x00 },		// 26 bei 0x01 Abnzeige verschoben ?!?!?
			// CHA_HSYNC_PULS_WIDTH 2C u. 2D
		//{ 0x2C, 0x2c }, // x19 0x27 },		// 25
		//{ 0x2D, 0x01 },		// 26 bei 0x01 Abnzeige verschoben ?!?!?
		{ 0x2E, 0x00 },		// 27
		{ 0x2F, 0x00 },		// 28
			// CHA_VSYNC_PULS_WIDTH x30 u. x31
		{ 0x30, 0x01 },		// 29
		{ 0x31, 0x00 },		// 30
		{ 0x32, 0x00 },		// 31
		{ 0x33, 0x00 },		// 32
			// CHA_HSYNC_HORIZONTAL_BACK_PORCH x34
		//{ 0x34, 0x010 }, // 0xdc },	x1c	// 33
		//{ 0x35, 0x01 },		// 34 x01
		{ 0x34, 0x04 }, // 0xdc },	x1c	// 33
		{ 0x35, 0x00 },		// 34 x01
		{ 0x36, 0x01 },		// 35
		{ 0x37, 0x00 },		// 36
			// CHA_HSYNC_HORIZONTAL_FRONT_PORCH x38,x39
			// { 0x38, 0x2B }, // 0x3C },		// 37
			// { 0x39, 0x01 },		// 38
		{ 0x38, 0x40 }, // 0x3C },		// 37
		{ 0x39, 0x00 },		// 38
			// CHA_VERTICAL_FRONT_PORCH x3A
		{ 0x3A, 0x28 },		// 39
		{ 0x3B, 0x00 },		// 40
#ifdef _LVDS_TEST_PATTERN_
		{ 0x3C, 0x10 },		// 41	CHA_TEST_PATTERN (0x10)
#else
		{ 0x3C, 0x00 },		// 
#endif	// _LVDS_TEST_PATTERN_
		{ 0x3D, 0x00 },		// 42
		{ 0x3E, 0x00 }    	// 43
	};

	// The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the 
	// recommended sequence defined in the datasheet

#endif	// _SN65DSI83_REG_




#ifdef _SN65DSI83_POR_
/*	
	SEG_XDATA U8 SN65_defaultConfiguration [SN65_NUM_WRITABLE_REG] [2] =   
	{	//  Address, Value
		{ 0x09, 0x00 },		// 01
		{ 0x0A, 0x05 },		// 02
		{ 0x0B, 0x10 },		// 03
		{ 0x0D, 0x00 },		// 04
		{ 0x10, 0x2e },		// 05
		{ 0x11, 0x00 },		// 06
		{ 0x12, 0x28 },		// 07
		{ 0x13, 0x00 },		// 08
		{ 0x18, 0x72 },		// 09
		{ 0x19, 0x00 },		// 10
		{ 0x1A, 0x03 },		// 11
		{ 0x1B, 0x00 },		// 12
		{ 0x20, 0x00 },		// 13
		{ 0x21, 0x05 },		// 14
		{ 0x22, 0x00 },		// 15
		{ 0x23, 0x00 },		// 16
		{ 0x24, 0x00 },		// 17
		{ 0x25, 0x00 },		// 18
		{ 0x26, 0x00 },		// 19
		{ 0x27, 0x00 },		// 20
		{ 0x28, 0xcf },		// 21
		{ 0x29, 0x01 },		// 22
		{ 0x2A, 0x00 },		// 23
		{ 0x2B, 0x00 },		// 24
		{ 0x2C, 0x01 },		// 25
		{ 0x2D, 0x00 },		// 26
		{ 0x2E, 0x00 },		// 27
		{ 0x2F, 0x00 },		// 28
		{ 0x30, 0x01 },		// 29
		{ 0x31, 0x00 },		// 30
		{ 0x32, 0x00 },		// 31
		{ 0x33, 0x00 },		// 32
		{ 0x34, 0x05 },		// 33
		{ 0x35, 0x00 },		// 34
		{ 0x36, 0x00 },		// 35
		{ 0x37, 0x00 },		// 36
		{ 0x38, 0x00 },		// 37
		{ 0x39, 0x00 },		// 38
		{ 0x3A, 0x00 },		// 39
		{ 0x3B, 0x00 },		// 40
		{ 0x3C, 0x00 },		// 41
		{ 0x3D, 0x00 },		// 42
		{ 0x3E, 0x00 }    	// 43
	};

*/
		/* ------------------------------------- 
		SN65DSI83 POR Default:
		Reg 0x09=0x00
		Reg 0x0A=0x0A
		Reg 0x0B=0x00
		Reg 0x0D=0x00
		Reg 0x10=0x3E
		Reg 0x11=0x00
		Reg 0x12=0x00
		Reg 0x13=0x00
		Reg 0x18=0x70
		Reg 0x19=0x05
		Reg 0x1A=0x03
		Reg 0x1B=0x00
		Reg 0x20=0x00
		Reg 0x21=0x00
		Reg 0x22=0x00
		Reg 0x23=0x00
		Reg 0x24=0x00
		Reg 0x25=0x00
		Reg 0x26=0x00
		Reg 0x27=0x00
		Reg 0x28=0x00
		Reg 0x29=0x00
		Reg 0x2A=0x00
		Reg 0x2B=0x00
		Reg 0x2C=0x00
		Reg 0x2D=0x00
		Reg 0x2E=0x00
		Reg 0x2F=0x00
		Reg 0x30=0x00
		Reg 0x31=0x00
		Reg 0x32=0x00
		Reg 0x33=0x00
		Reg 0x34=0x00
		Reg 0x35=0x00
		Reg 0x36=0x00
		Reg 0x37=0x00
		Reg 0x38=0x00
		Reg 0x39=0x00
		Reg 0x3A=0x00
		Reg 0x3B=0x00
		Reg 0x3C=0x00
		Reg 0x3D=0x00
		Reg 0x3E=0x00
		------------------------------------- */
#endif // _SN65DSI83_POR_

/*============================================================================
Prototype definitions
============================================================================*/


U8 readSN65Register (U8 I2Creg) ;

// extern


/*============================================================================
Function Definitions
============================================================================*/

/*============================================================================
Name	:   readSN65Register()
------------------------------------------------------------------------------
@brief  Reads a 8 bit value from the specified SN65DSI83 register
			
@Input:	I2C Register Nummer
@Output:	none
@Return: 1 Byte Register value
@Notes:	none
============================================================================*/

U8 readSN65Register (U8 I2Creg) {
	register U8 value ;

	SM_Send (SN65DSI83_SLAVE_ADDR, I2Creg) ;	// IIC Adresse setzen
	value = SM_Receive (SN65DSI83_SLAVE_ADDR, READ_1_BYTE) ;
	return ( value ) ;
}

/*============================================================================
Name	:   readSN65Register()
------------------------------------------------------------------------------
@brief  Reads a 8 bit value from the specified SN65DSI83 register
			
@Input:	I2C Register Nummer
@Output:	none
@Return: 1 Byte Register value
@Notes:	none
============================================================================*/

/*void writeSN65Register (U8 I2Creg, U8 value) {

	SM_Send_2B (SN65DSI83_SLAVE_ADDR, I2Creg, value) ;	// IIC Adresse setzen
}*/

/*============================================================================
Name	:   printSN65Register ()
------------------------------------------------------------------------------
@brief  SN65DSI83 Regsiter aulesen und ausgeben..
 Default Register ermittelt mit TI DSI-Tuner 
 siehe: CSR-Tianma-TM101JVHG32-01.txt
@Input:	ucMode
@Output:	none
@Return:	none
@Notes:	none
============================================================================*/

void printSN65Register (void) {

#ifdef _SN65DSI83_REG_
	SEG_XDATA U8 i ;	
	SEG_XDATA U8 iReg ;
	SEG_XDATA U16 iVal ;
	SEG_XDATA U8 ucTmp[6] ;

	putstr (TRENNLINIE);
	putstr ("SN65DSI83 Register\r");
	 
	for (i = 0; i < SN65_NUM_WRITABLE_REG; i++)
	{ 
		iReg = SN65_defaultConfiguration[i] [0] ;
		iVal = readSN65Register (iReg) ;

		putstr ("Reg 0x") ;
		put2Hex2Buffer (ucTmp, iReg) ;
		putstr (ucTmp);
		putstr ("= 0x") ;
		put2Hex2Buffer (ucTmp, (U8) (iVal)) ;
		putstr (ucTmp);
		putstr ("\r");
	}
	putstr (TRENNLINIE);
#endif	// _SN65DSI83_REG_
}

/*============================================================================
Name	:   setSN65Register ()
------------------------------------------------------------------------------
@brief  .
@Input:	ucMode
@Output:	none
@Return:	none
@Notes:	none
============================================================================*/
void setSN65Register  (U8 ucMode) {
	SEG_XDATA U8 i ;	
	SEG_XDATA U8 uReg ;
	SEG_XDATA U8 uVal ;
	SEG_XDATA U8 ucTmp[6] ;

	if (ucMode > 0) 	{
		putstr ("set SN65DSI83 Register: ");

			// set SOFT_RESET bit to 1
		// Eintrag 00=Reg 0x09
		//uReg = SN65_defaultConfiguration [0x00] [0] ;
		//uVal = SN65_defaultConfiguration [0x00] [1] ;
		//uVal |= 0x01 ;
		//SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		
	//	delay_ms (SPAXT_20MSEK) ;		


		// set PLL_EN bit to 0: Reg 0x0D.0 = 0 PLL disable
		// Eintrag 03=Reg 0x0D

		uReg = SN65_defaultConfiguration [0x03] [0] ; 	// reg nr
		uVal = SN65_defaultConfiguration [0x03] [1] ;	// re value
		uVal &= 0xFE ;
		SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		delay_ms (SPAXT_20MSEK) ;


	

		// min. 3ms warten
		//delay_ms (SPAXT_10MSEK) ;

		for (i = 1; i < SN65_NUM_WRITABLE_REG; i++)
		{ 
			uReg = SN65_defaultConfiguration [i] [0] ;
			uVal = SN65_defaultConfiguration [i] [1] ;
			//writeSN65Register (uReg, uVal) ;
			SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		}
		putstr ("..done.\r");

		printSN65Register () ;

		// min. 3ms warten
		delay_ms (SPAXT_10MSEK) ;

		// The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the 
		// recommended sequence defined in the datasheet

		// set PLL_EN bit to 1: Reg 0x0D.0 = 1
		// Eintrag 03=Reg 0x0D
		uReg = SN65_defaultConfiguration [0x03] [0] ;
		uVal = SN65_defaultConfiguration [0x03] [1] ;
		uVal |= 0x01 ;
		SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		// min. 3ms warten
		delay_ms (SPAXT_10MSEK) ;

		// set SOFT_RESET bit to 1
		// Eintrag 00=Reg 0x09
		uReg = SN65_defaultConfiguration [0x00] [0] ;
		uVal = SN65_defaultConfiguration [0x00] [1] ;
		uVal |= 0x01 ;
		SM_Send_2B (SN65DSI83_SLAVE_ADDR, uReg, uVal) ;	// IIC Adresse setzen
		delay_ms (SPAXT_10MSEK) ;

		// clear Error Register
		#define ERROR_REG	0xE5

		SM_Send_2B (SN65DSI83_SLAVE_ADDR, ERROR_REG, 0xFF) ;// IIC Adresse setzen
		
		delay_ms (SPAXT_2MSEK) ; //delay 2 ms	
		// read error Register
		
		uReg = ERROR_REG ;
		uVal = readSN65Register (uReg) ;
//printSN65Register 
		putstr ("Error Reg 0x") ;
		put2Hex2Buffer (ucTmp, uReg) ;
		putstr (ucTmp);
		putstr ("= 0x") ;
		put2Hex2Buffer (ucTmp, uVal) ;
		putstr (ucTmp);
		putstr ("\r");
	}	
}

/*============================================================================
Name	:   eeeT()
------------------------------------------------------------------------------
@brief  .
@Input:	none
@Output:	none
@Return:	none
@Notes:	none
============================================================================*/
/*void eeeT (void) {
	
}*/

/*============================================================================
  END OF FILE
============================================================================*/

can you tell me the DSI source and so on. I could not understand that.

I am waiting for your reply.

Thank you.

Best regards,

Rajat Barmon

0 Rajat Barmon1 over 4 years ago in reply to Rajat Barmon1

Intellectual 350 points

Dear I.k,

1.We have no DSI / MIPI Lanes connected to the SN65DSI EVAL Board.

2.How to test the LVDS Output without DSI Lanes connected to the eval board and the test pattern clocked only with the reference clock.

can you tell something ?

regards,

Rajat Barmon

0 Rajat Barmon1 over 4 years ago in reply to Rajat Barmon1

Intellectual 350 points

Dear I.K,

I am not using the any input connector (J4,J1).Only using J6 (LVDS ChA Samtec connector). Please see the Picture.

This is the hardware setup.

I am waiting for your reply.

Regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

If you're just using the test pattern then it's fine to not provide DSI CLK/Data if you're using a reference clock. Here is an example:

Since you're using J6 you should make sure you're connecting CHA instead of CHB, as this connector has both channels.

Also, are you using the on-board reference clock on the EVM or an external reference clock that is not on the EVM?

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.K,

I am using on board Ref clock. So, Is it necessary to connect the DSI input (J4 or j1) for channel A?

How could i get the LVDS output?

Thanks,

Regards,

Rajat

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

It's not necessary to connect J4 or J1 if there is no DSI input. I am saying to make sure that you have connected the correct signals on J6, as this connector has signals for both LVDS CHA and LVDS CHB.

Additionally, since you're using the onboard REFCLK, did you program it to be the 65 MHz your settings say? The default frequency is 27MHz, and it needs to be programmed separately to change it to a different value as the DSI-Tuner will only generate settings for the DSI83. Another option is to use the REFCLK multiplier setting in the DSI-Tuner to try and get the frequency close to what you want it.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Hi I.k,

Can you check my. Txt file from few conversation back. I am getting the right frequency from the board. But display is not coming somehow.

Regards,

Rajat

0 Rajat Barmon1 over 4 years ago in reply to Rajat Barmon1

Intellectual 350 points

Dear I.K,

I fixed the PLL locked problem.But still I did not get the Display! Can you tell me which will be the next steps? I fixed the right parameters for display in the dsi tuner and set to the register.. Can you check my .txt file?

I am waiting for your reply.

regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

I can't help check your code but I can help check the register settings. Please attach the .dsi file from the DSI-Tuner as well as your display panel's datasheet.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.K,

Thank you for your reply. I did not attached the .dsi file, Hence, I made a screen shoot and the display data sheet.

N.B: I fixed the reference clock 68.2Mhz (According to the dispaly datasheet).

TM101JVHG32-01_Datasheet.pdf

Page No. 10 and 11 will be helpful information for settings the panel Datasheet.

I am waiting for you reply.

Best regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Most of those settings look okay. However, if you are using the REFCLK then "LVDS CLK source" in the DSI section should be "Ref CLK".

Additionally, since you're not connecting any DSI input and just trying the test pattern, then you should also select the "Test Pattern" box in the first tab.

Fix these items in the DSI-Tuner then regenerate the CSR text file again.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Hi I.K,

Thank you for your reply. I have attached the screen shoot of the Settings. Still I am not getting the right combination color. Please see the attachment.

1. I did not understand why the output windows indicating the cross signed ?

2. Is this right configuration ? I think So,

3. May be this is the sync problem ? what do you think ? How can i overcome the problem ?

I am waiting for your reply. Thank you.

Regards,

Rajat Barmon

0 Rajat Barmon1 over 4 years ago in reply to Rajat Barmon1

Intellectual 350 points

Dear I.k,

I got this display with existing setup. That was the connection problem. But it is seems okey. but not exactly i am getting. How I can get the right display. Please see the Display.

I am Waiting for your reply.

Thank you.

Best regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Sorry for the delay. Is that image supposed to be the test pattern from the DSI83? Are you absolutely certain you fixed the connection problems and have the channels mapped correctly?

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Hi I.K,

Yes! It supposed to be test pattern from SN65. May be the connection Problem. Moreover,I am using only one channel (Ch-A). I could not understand,how I resolve the problem? Do you have an idea?

I am waiting for your reply.

Regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Please make sure your connections are correct. I mentioned before that the connector you're using has pins for both channel A and channel B, so you need to be careful and ensure that you're mapping the correct channel with the lanes in the correct order to your display.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.K,

Thank you for your reply. I said you that I am using only one channel (Ch-A). I ignored Ch-B. The connection seems right. But it is not coming.

do you have any idea ?

I am waiting for your reply.

Best regards,

Rajat Barmon

0 Rajat Barmon1 over 4 years ago in reply to Rajat Barmon1

Intellectual 350 points

Dear I.K,

Can you tell me if i want to use the DSI Input, what will be my parameter to set the input.Such as CLK and so on.I am using Tianma Displa. I already attached my datasheet of Display.

Can you give me the link where it is describing about DSI input?

I am waiting for your reply.

Thank you.

Best regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Please follow the steps in this training video: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-single-link-lvds-operation

For the DSI source you need to make sure the input matches what you configured in the DSI83 (active pixels, blanking pixels, DSI CLK frequency, etc).

You also need to make sure to follow the initialization sequence in the datasheet.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.K,

Thank you for your reply. I tried with J2 instead of J6 connector with reference clock for checking the probelm ! I am getting the same problem. Here are my displays.1st Image is for J2 and 2nd is for J6.

May be the problem is same for both connector.May be the problem is RGB color code. I am getting the LVDS Frequency 68.2 MHz as I expected. Even there is nothing describe in register settings for RGB color.Do you have any Idea ? I cannot go further without solve this problem. I am facing this problem since last month. Please help me !

I am waiting for your reply.

Best Regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

The 2nd picture looks more correct aside from the intensity change in the color in the middle of the panel, which shows up in both pictures. There's nothing wrong with the connectors on the EVM and there's no problems with the RGB code from the DSI83.

Can you try changing register 0x19.3:2 to 11 to increase the LVDS voltage output swing to see if that helps?

Other than that, the only other explanation is that the issue is with the panel or with the connection on the panel.

Regards,

I.K.

0 Rajat Barmon1 over 4 years ago in reply to Ikechukwu Anyiam

Intellectual 350 points

Dear I.K,

Thank you for your reply. I resolved the problem.

Now, Can you tell me how I can set the DSI Input ?

I am waiting for your reply.

Thank You.

Best Regards,

Rajat Barmon

0 Ikechukwu Anyiam over 4 years ago in reply to Rajat Barmon1

TI__Mastermind 35130 points

Hi Rajat,

Was the issue related to your connection?

For the DSI input you should configure your source so that it outputs the same timing parameters you configured the DSI83 with (i.e. the active/blanking pixels, clock frequency, etc.)

Also, ensure that you follow the initialization sequence in the datasheet.

Regards,

I.K.

Interface

Interface forum

SN65DSI83: Register settings configuration in SN65SDI83 for the Test Pattern