SN65DSI83: LVDS output clock duty cycle adjustment

Hi Kevin,

Unfortunately there's not a way to adjust the duty cycle of the LVDS output clock. Does your DSI clock also have this symmetry issue?

Regards,

I.K. 

The DSI clock is dead-on 50/50. Are there any other register settings that might indirectly affect the duty cycle of the LVDS clock? Have you ever had anyone run into this issue with this chip before?

Thanks,

Kevin

Hi Kevin,

There aren't any registers that can affect the LVDS clock duty cycle, and I haven't seen anyone else have this issue. Since the DSI clock's duty cycle is fine, I wonder if it's just a routing issue with the clock lanes. Can you share your layout with me at i-anyiam@ti.com?

Regards,

I.K. 

Hi I.K.

Yes, just sent the layout to your e-mail. Please let me know if you see anything in the routing that might cause the issue.

Thanks,

Kevin

Hi Kevin,

The routing looks okay, but one issue I see is that you are missing 100ohm differential termination resistors on the SN65LVDS4 LVDS inputs. This will need to be corrected, but I don't think it's what's causing the duty cycle distortion. 

Can you fill out the settings you're using for the SN65DSI83 into the DSI-Tuner tool and send me .dsi output file? Here is a guide for the tool: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-single-link-lvds-operation 

And just press Ctrl+E to export the file after filling your settings in.

Regards,

I.K. 

I just e-mailed you the .dsi output for the settings we're using.

Can you clarify how the LVDS pairs should be terminated for the different near-end termination settings on the DSI chip? We have near-end termination set to 200-ohm (default). Should the on-board termination resistors at the SN65LVDS inputs be 100-ohm regardless of the near-end termination setting on the DSI chip, or should they match the DSI chip's setting?

Thanks,

Kevin

For the DSI83 I've found the near-end termination does not really matter much. The default is 200-ohms and it's fine to keep it as such. The on-board termination on the SN65LVDS94 needs to be 100-ohm, yes. If the DSI83 was connected to an LVDS panel instead of the LVDS94, the LVDS panel would have integrated 100-ohm termination resistors on the input lanes.

Regards,

I.K. 

The settings you're using look okay. Can you confirm the following:

1. The initialization sequence for the SN65DSI83 on page 15 is being followed

2. See if any error bits are getting set in register 0xE5 (clear this register by writing 0xFF to it before reading from it)

Regards,

I.K.

We were not waiting 10ms after the soft reset before sending out DSI data. We added a delay to meet that requirement, but it didn't seem to affect anything. We also read out the contents of the 0xE5 register (after writing 0xFF to it) and it was 0x00, so no error bits are getting set.

The LVDS output clock still has a distorted duty cycle, and the display still has the poor quality image on mid-scale gray screens.

-Kevin

Hi Kevin,

Have you tried swapping the DSI83 out with another unit?

Regards,

I.K. 

Yes, we built up 5 prototypes and they all behave the same way.

Hm the only other thing I can think of is an issue with the DSI clock. Can you try using an external REF CLK to generate the LVDS CLK instead of the DSI CLK?

Regards,

I.K.