DS90UB941AS-Q1: ESD Contact Discharge test fail（8kV)

Regarding the serializzer, 941as design is similar as 947 or 949, you can care for the high speed design guideline here. for chip level, no register is helpful to reduce the system-level emc design. if you use the external clock, you also need pay attention this clock design.

• Board Stack-up

– 4 layer board minimum

– Dedicated ground and power planes (do not mix signal and ground/power layers)

– Ground pour on top layer, evenly spaced around differential traces

• Single-ended inputs/outputs

– Keep away from differential traces (>2x trace width spacing)

– Unused inputs should not float – tie to GND or VDDIO with resistor (~10kΩ)

– 50Ω (single-ended) traces recommended

– Inline resistors to limit edge rates and ringing (25Ω to 33Ω typical)

– Minimize trace length/load, bury longer traces (>50mm) in inner layer

• Power

– Match power and ground plane sizes

– Use effective decoupling and bypassing elements (multiple value decades) placed as

close as physically possible to the device (<10mm)

– Use recommended ferrite bead filters

High-speed FPD-Link II/III signal pair

– 100Ω (±10% total) differential coupled traces (priority)

– Minimized intra-pair skew (secondary)

– Minimize stubs and taps

– Use common-mode choke – DLW21SN900HQ2L recommended

– Small-size (0603 or smaller) AC-coupling capacitors to minimize pad discontinuity

– For short traces to connector (<50mm): no vias, place signal pair together on surface

layer)

– For longer traces to connector (>50mm): bury trace in inner signal layer

– 45-degree corners ok, rounded corners best, no asymmetric meanders

– Continuous ground plane underneath traces to connector

– Lump discontinuities together (CM choke, AC-coupling, vias) near device or near

connector (not near middle)

– Avoid crossing polarity using vias

– Keep away from noise sources (power and single-ended traces) with >2x trace width

spacing

– ESD elements (optional) ≤0.8pF typical loading

best regards,

Steven