DP83848I: Reset timing consult

Lin_Charles

Part Number: DP83848I

Hi team,

My customer want to use DP83848I as below,

In RMII mode, they want to use reset signal to control the clock generator to the PHY and MCU. When power up, reset will HIGH, and clock will apply to PHY. Do you think any risk to such application? Thanks.

BR,

Charles Lin

over 5 years ago

0 Lin_Charles over 5 years ago

TI__Expert 4260 points

Hi team,

Do you have any updates about this thread? Thanks.

BR,

Charles Lin

0 Cecilia Reyes over 5 years ago in reply to Lin_Charles

TI__Genius 9920 points

Hi Charles,

Apologies for the delay. You sent us this email over the weekend outside of our 24 hour response window. I am having trouble following in your diagram as it does not show anything about RESET.

Are you trying to only turn the CLK on when RST is high? I believe the clock must be stable before RST is pulled high. Refer to the power up timing diagram for more information.

Thanks

Cecilia

0 Lin_Charles over 5 years ago in reply to Cecilia Reyes

TI__Expert 4260 points

Hi Cecilia,

Thank you for your response here. YES, customer wants to turn the CLK on when RST is high. This RST is also used for PHY reset. After reset pin HIGH, I will let them reinitialize PHY register, this can do normall communication now. I believe this meet the power up requirements. Please help confirm if it is ok? Thanks.

BR,

Charles Lin

0 Lin_Charles over 5 years ago in reply to Lin_Charles

TI__Expert 4260 points

Hi Cecilia,

Can you please help look into this case again? Customer may need team's confirmation about the setting I mentioned above. Thanks.

BR,

Charles Lin

0 Cecilia Reyes over 5 years ago in reply to Lin_Charles

TI__Genius 9920 points

Hi Charles,

The clock must be present before power on and reset. The clock can not be powered by the Reset, meaning they both go high at the same time.

Thanks,

Cecilia

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DP83848I: Reset timing consult