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Differential to single ended

Avi Loschak
Prodigy 90 points
Other Parts Discussed in Thread: DSLVDS1001, DSLVDS1048, SN65LVDS4

I am trying to find a differential to single ended driver that meets the following specs: 3.3V output (single-ended), 100MHz clock frequency, can handle >45pF of distributed load capacitance, and has a rise time of 0.7nS. I tried using the parametric search but was unsuccessful in finding one.

Thank you,
Avi

  • 0
    TI__Guru* 93670 points

    Hi Avi,

    I am thinking perhaps DSLVDS1001 may meet your requirements. Please note data sheet below.

    http://www.ti.com/lit/ds/symlink/dslvds1001.pdf

    Regards,, Nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 90 points

    Hi Nasser,

    Thank you for your quick reply. I don't think this will work as it goes the wrong way. I am trying to generate the single ended LVCOMS/LVTTL signal from a differential stimulus. I need to drive something single-ended'ly, not the other way around.

    Do you have any other ideas?

    Thank you.

    Avi

  • 0 in reply to Avi Loschak
    TI__Guru* 93670 points

    Hi Avi,

    Please take a look at DSLVDS1048. This the receiver side.

    http://www.ti.com/lit/ds/symlink/dslvds1048.pdf 

    Please note rise/fall time worst case is 1nS with CL of 15pF. I am not able to find a part to meet max 0.7ns with CL of >45pF.

    Regards,, Nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 90 points

    Hi Nasser,

    Thank you again for your reply. This does look like a good device minus the worst case for rise/fall time. Typically, can we rely on the the Typ spec or do we assume it will run with the Max spec? Also, when it says it can be loaded with 15pF, is that assuming a lumped load or distributed load? Maybe it can drive a bigger capacitive load if it's distributed across multiple traces and PCBs. What do you think?

    Lastly, given that I am extremely tight on space, if I am limited to these specs, do you know of the same part with just one input/output? The smaller the IC the better.

    Thanks again, Nasser. I appreciate the help.

    Avi

  • 0 in reply to Nasser Mohammadi
    Prodigy 90 points

    Nasser, looking further into it, what about SN65LVDS4? That has a rise/fall time of 550pS and outputs a 3.3V LVCMOS/LVTTL signal. This too however was only tested up to C_LOAD = 10pF. 

    Any thoughts?

  • 0 in reply to Avi Loschak
    TI__Mastermind 43795 points

    Hi Avi,

    All of these devices are tested with a distributed load.  The distributed load test environment is a single-ended 50 Ohm impedance trace.  At the end of the trace we typically use a SMA connection cabled to a high-bandwidth oscilloscope to make the rise/fall measurement. 

    What does your 45pf load look like?  Is it multiple device loads connected along a 50 Ohm transmission line of some length?

    Many of these devices have IBIS models.  IBIS would be a good tool to use to understand how the 3.3V output will interact with your specific distributed load.

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Prodigy 90 points

    Hi Lee,

    That makes sense. I guess normally having 10pF is not generally seen.

    My 45pF load is just there because of all of the interconnects the signal would have to go through. It goes through 2 PCBs, a flex cable, and multiple connectors. When I calculated the capacitance of the traces and added them all up (not including whatever the connectors added) I got around 44/45pF.

    Good idea with the IBIS model. I'll mess around with it.

    Thanks!

    Avi

  • 0 in reply to Avi Loschak
    TI__Mastermind 43795 points

    Hi Avi,

    Sounds like you will be okay as long as there is just a single device load at the far end.

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Prodigy 90 points

    Hi Lee,

    Can you explain why you think it'll be okay? I know there is only just device load (an ASIC Hi-Z pad) on the far end, but the load is still highly capacitive given all of the interconnects.

    Also, if you don't mind answering this, do you have any suggestions on how to terminate at the load given that it is Hi-Z?

    Thanks,

    Avi

  • 0 in reply to Avi Loschak
    TI__Mastermind 43795 points

    Hi Avi,

    Sorry for the delay.  This type of signaling technique has been widely used for many older single ended technologies.  I hope the IBIS modeling has helped you to see how the signal and Hi-Z ASIC input interact.

    The Hi-Z receiver creates a reflection at the end of the transmission line.

    Here is the sequence of events.

    1. At a LVCMOS Tx with a 50 Ohm impedance the transmit waveform will achieve an amplitude of VDD/2.

    2. At the ASIC Rx the Hi-Z impedance will result in a reflection coefficient of 1 at the end of the transmission line.

    3. Due to the reflection the ASIC will see an amplitude of VDD.

    4. The 50 Ohm impedance of the LVCMOS driver becomes the termination as the reflection returns from the ASIC input.

    Regards,

    Lee