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DS280DF810: Jitter performance

Taketo Sato
Genius 10315 points
Part Number: DS280DF810

Hello team,

I would like to know how much jitter will be added to clock input.

DS280DF810 datasheet figure20 shows eye diagram.

Could you please let me know how the eye is measured?

Is it got with using the external 25MHz as trigger of sampling oscilloscope?

or using clock recovery in sampling oscilloscope?

Best regards,

  • 0
    TI__Mastermind 19235 points

    Hi Taketo-san,

    The 25 MHz calibration clock does not feed into the high-speed data path. Because of it, the CAL_CLK_IN jitter requirements are not very stringent. This calibration clock mainly serves as a reference for the low-speed digital logic. Th DS280DF810 implements a reference-less CDR architecture, so the clock is recovered from the high-speed data and then used for retiming function.

    With regard to figure 20 on the datasheet, this eye diagram was measured using a Keysight DCA-X with clock and data recovery module. The CDR loop bandwidth is configured to align with the interface standard in question.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 10 points

    Dear Rodrigo-san,

    I want to use DS280DF810 (and its successor) as PRBS generator and PRBS checker.
    There is no plan to use this LSI as a retimer.
    In this case, please tell me how the operating frequency of the device is determined.

    Best regards,

    Takashi Kusaka

  • 0 in reply to Takashi Kusaka
    TI__Mastermind 19235 points

    Hi,

    If the user is operating the channels in retimed mode then the CDR rate needs to be configured via either standard mode (i.e. channel register 0x2F) or manual mode (i.e. channel registers 0x60 thru 0x63.) Refer to the TI retimer programming guide for details. You may request download access to retimer programming guide via the TI.com product page for DS280DF810.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer