Other Parts Discussed in Thread: DP83630
Hello team,
I hope all is well!
I am evaluating the possibility of implementing the synchronization function (10MHz 1PPs) on one of our GPS receivers through the PTP protocol on the 10 / 100Mbps Ethernet network; thus I'm considering the DP83640, Physical 10/100, which supports the mechanisms for synchronization SyncE 1588.
The analysis of the data sheet in these days has convinced me to deepen the discussion. However, some doubts arise about how to implement the entire system and I would need some clarification on the merits.
From the technical documentation related to the device it seems that the Phy in question is able to independently manage the synchronization of its clock with a mechanism internal to the device as illustrated in figure 2 of the AN-2006.
The TI site presents a demo with 2 interface boards containing the simple DP83640 and little else; but the Master and Slave of the system seem to be managed by a mysterious device connected to the MAC and implemented in FPGA.
What is done in FPGA I can't find any trace of it, nor of source code to pass to our software developers.
We are currently trying to understand how to implement the synchronization protocol as the documentation that I managed to find on the website is by no means exhaustive and I suspect that the entire stack is quite complex.
There were several implementations with various microcontrollers based on your devices but today these demos seem nowhere to be found.
Please In the meantime, if you have some material on the Sync-E synchronization problem and on the PTP protocol, I could certainly start studying them.
Could you please let me know were to look for further collateral?
Thank you and best regards,
Adrian
