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XIO2001: XIO2001 power up problem

Yossy Goldenberg
Prodigy 240 points
Part Number: XIO2001

Hello,

I have a design with XIO2001 which I have designed based on TI's EVM board and I a have power-up issue with my board:

Since i need it as a simple PCIe To PCI bridge, i do not use a EPROM to configure the device. Based on the EVM board ("Pin 9 on the J1 header is a global reset (GRST ) for the XIO2001. Driving this pin low will cause all registers and state machines within the XIO2001 to return to a default power-up state. This pin generally must remain disconnected.")  and based on the implementation guide :("During an XIO2001 device power-up from the D3cold power state, there is no requirement to assert this terminal low"), i have left GRST  pin floating.

While turning on the PC, it's seems that the PC freezes. The PERSTN signal goes from low to high while turning on  the PC.  If I am asserting and deasserting  (gnd to 3.3V) the PERSTN signal manually  then,  the PC continues with it's boot, but in device manager the bridge comes up with code 12. I have tried it on several PCs. 

I have also tried to add some delay to the PERSTN signal, with no change.

I have tried some of the solutions in the support forums with no success. 

Please advise,

Regards,

Yossy Goldenberg

  • 0
    TI__Expert 8165 points

    Hello Yossy,

    Could you please share your schematic so that we can review?

    Can you check the power-up sequence and ensure it follows the recommendations provided in the datasheet?

    Regards,

    Davor

  • 0 in reply to Davor Glisic
    Prodigy 240 points

    Hello Davor,

    Thank you for your replay and support.

    Enclosed please find my schematic for the XIO2001. My design is based on TI's EVM board, where the GRSTN is not connected. I have tried to add a capacitor to that signal and manage to crate the power-up sequence as in page 22 in the datasheet (currently, due to the Corona, we are working from home, and I cant send a scope image), 

    Please note that I have shorted signals SCL and SDA . They are floating in the schematic.

    bridge.pdf

  • 0 in reply to Yossy Goldenberg
    TI__Expert 8165 points

    Hello Jossy,

    The following are my comments on the schematic:

    -The VDD_15_PLL pin must be isolated from the rest of the VDD_15 pins.

    -GPIO4/SCL must be pulled low if the external EEPROM is not required (looks like you already addressed this).

    -GRST# must follow the power-up sequence described in the datasheet.  TI EVM does not follow this requirement and still works fine.  However, we've seen feedback from the customers having issues due to noisy power rails that they were able to fix the issues by the meeting the GRST# timing.

    Regards,

    Davor

  • 0 in reply to Davor Glisic
    Prodigy 240 points

    Hello Davor,

    Thank you very mach for your help.

    My design is based on the EVM rev C files from the following forum discussion: https://e2e.ti.com/support/interface/f/138/p/709955/2617061#2617061?jktype=e2e from the XIO2001 Support & training web page. In those files the PLL is not filtered. In the EVM web page, the link to the EVN schematic say it's Rev B while  it actually rev D, but I didn't check it before, since I was sure that Rev C is newer than Rev B...My mistake.

    I intend to do a new layout. Can you, please, recommend for a pi filter inductor other then the one in the EVM, which is  big for my design and no so popular?  Are there any other recommendation for the inductor except for the 200 mA and 220 Ohms @ 100Mhz?

    Thank you for your kind help.

    Regards,

    Yossy Goldenberg

     

  • 0 in reply to Yossy Goldenberg
    TI__Expert 8165 points

    Hello Yossy,

    Other than the current rating and the 220-ohm impedance at 100 MHz, the inductor should have 50-miliohm or lower DCR. 

    Regards,

    Davor

  • 0 in reply to Davor Glisic
    Prodigy 240 points

    Hello Davor,

    Thank you very mach for your support!

    Yossy